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X40430S14-C Datasheet(PDF) 8 Page - Intersil Corporation |
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X40430S14-C Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 26 page 8 FN8251.1 May 24, 2006 Figure 2. Two Uses of Multiple Voltage Monitoring Figure 3. VTRIPX Set/Reset Conditions WATCHDOG TIMER The Watchdog Timer circuit monitors the microproces- sor activity by monitoring the SDA and SCL pins. A standard read or write sequence to any slave address byte restarts the watchdog timer and prevents the WDO signal going active. A minimum sequence to reset the watchdog timer requires four microprocessor instructions namely, a Start, Clock Low, Clock High and Stop. The state of two nonvolatile control bits in the Status Register determine the watchdog timer period. The microprocessor can change these watch- dog bits by writing to the X40430, X40431, X40434, X40435 control register (also refer to page 20). Figure 4. Watchdog Restart V1, V2 AND V3 THRESHOLD PROGRAM PROCEDURE (OPTIONAL) The X40430 is shipped with standard V1, V2 and V3 threshold (VTRIP1, VTRIP2, VTRIP3) voltages. These values will not change over normal operating and stor- age conditions. However, in applications where the standard thresholds are not exactly right, or if higher precision is needed in the threshold value, the X40430, X40431, X40434, X40435 trip points may be adjusted. The procedure is described in the following situation, and uses the application of a high voltage control sig- nal. 6-10V VCC 5V V3MON X40431-A Unreg. Supply VCC X40431-B RESET V2FAIL System VCC Reset V2FAIL V3FAIL System Reset Notice: No external components required to monitor three voltages. 1M V3MON V3FAIL V2MON 5V Reg 3.0V Reg 1.8V Reg 3.3V 390K V2MON RESET Power Fail Interrupt VCC (1.7V) VCC/V2MON/V3MON VTRIPX VP tWC A0h 0 7 70 7 0 SCL WDO SDA (X = 1, 2, 3) 00h SCL SDA .6µs 1.3µs WDT Reset Start Stop X40430, X40431, X40434, X40435 |
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