5

FN8243.1

April 17, 2006

STOP Condition Hold Time

From SDA rising edge to SCL falling edge. Both

crossing 70% of VDD

600

ns

Output Data Hold Time

From SCL falling edge crossing 30% of VDD,

until SDA enters the 30% to 70% of VDD

window

0ns

SDA and SCL Rise Time

From 30% to 70% of VDD

20+

0.1*Cb

250

ns

SDA and SCL Fall Time

From 70% to 30% of VDD

20+

0.1*Cb

250

ns

Cb

Capacitive Loading of SDA or SCL

Total on-chip and off-chip

10

400

pF

Rpu

SDA and SCL Bus Pull-Up Resistor

Off-Chip

For Cb = 400pF, max is about 2~2.5k

Ω

For Cb = 40pF, max is about 15~20k

Ω

1k

Ω

WP Setup Time

Before START condition

600

ns

WP Hold Time

After STOP condition

600

ns

NOTES:

8.

for i = 16 to 111, and T = -40°C to 85°C

7F hex, respectively.

12.

; for i = 1 to 111, and T = -40°C to 85°C

write cycle.

14. Parameter is not 100% tested.

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

(Note 1)

MAX

UNIT

TC

V

Max V RW

()i

() Min V RW

()i

()

–

[]

Max V RW

()i

() Min V RW

()i

()

+

() 2

⁄

-----------------------------------------------------------------------------------------------

10

6

125

°C

-----------------

×

=

TC

R

Max Ri

() Min Ri

()

–

[]

Max Ri

() Min Ri

()

+

[] 2

⁄

----------------------------------------------------------------

110

6

×

125

°C

-------------------

×

=

SCL

SDA

(INPUT TIMING)

SDA

(OUTPUT TIMING)

ISL96017