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FIN12ACGFX Datasheet(PDF) 7 Page - Fairchild Semiconductor

Part # FIN12ACGFX
Description  uSerDes Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FIN12ACGFX Datasheet(HTML) 7 Page - Fairchild Semiconductor

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© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN12AC Rev. 1.1.0
7
Deserializer Operation Mode
The operation of the deserializer is only dependent upon the data received on the DSI data signal pair and the CKSI
clock signal pair. The following two sections describe the operation of the deserializer under two distinct serializer
source conditions. References to the CKREF and STROBE signals refer to the signals associated with the serializer
device used in generating the serial data and clock signals that are inputs to the deserializer.
When operating in this mode, the internal serializer circuitry is disabled, including the parallel data input buffers. If there
is a CKREF signal provided, the CKSO serial clock continues to transmit bit clocks. When S1 and S2 are asserted low,
all CMOS outputs are driven low at the output of the deserializer.
When the DIRI signal is asserted LOW, the device is configured as a deserializer.
Data is captured on the serial port and deserializer through use of the bit clock
sent with the data. The word boundary is defined in the actual clock and data sig-
nal. Parallel data is generated at the time the word boundary is detected. The fall-
ing edge of CKP occurs coincident with the data transition. The rising edge of
CKP is generated approximately seven bit times later. When no embedded word
boundary occurs, no pulse on CKP is generated and CKP remains HIGH.
Figure 6. Deserializer Timing Diagram (Serializer Source: CKREF equals STROBE)
The logical operation of the deserializer remains the same if the CKREF is equal
in frequency to the STROBE or at a higher frequency than the STROBE. The
actual serial data stream presented to the deserializer differs because it has non-
valid data bits sent between words. The duty cycle of CKP varies based on the
ratio of the frequency of the CKREF signal to the STROBE signal. The frequency
of the CKP signal is equal to the STROBE frequency. The falling edge of CKP is
coincident with data transition. The LOW time of the CKP signal is equal to 1/2
(seven bit times) of the CKREF period. The CKP HIGH time is equal to STROBE
period – half of the CKREF period. Figure 7 is representative of a waveform that
could be seen when CKREF is not equal to STROBE. If CKREF is significantly
faster, additional non-valid data bits occur between data words.
Figure 7. Deserializer Timing Diagram (Serializer Source: CKREF does not = STROBE)
WORD n-1
WORD n+1
WORD n
b12 b13 b14 b1 b2
b3 b4 b5 b6
b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17
WORD n-2
DP[1:12]
CKP
CKSI
DSI
WORD n
WORD n-1
WORD n-1
~7 bit times
WORD n+1
WORD n
b1
b12 b13 b14
b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14
WORD n-2
DP[1:12]
CKP
CKSI
DSI
WORD n
WORD n-1
Deserializer Operation: (Figure 6)
DIRI = 0
(Serializer Source:
CKREF = STROBE)
Deserializer Operation: (Figure 7)
PwrDwn = 1
DIRI = 0
(Serializer Source:
CKREF does not = STROBE)


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