7

FN8220.3

March 8, 2006

t

D

1

D

3

Programmable

Width and Polarity

Analog

Video In

P

1

P

2

P

3

P

4

P

5

P

6

P

7

P

8

P

0

P

9

D

0

R

HS

OUT

P

10

P

11

P

12

D

2

The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.

The sampling phase setting determines its relative position to the rest of the AFE’s output signals

DATACLK

R

HSYNC

IN

The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.

HSYNC

FIGURE 5. 48 BIT OUTPUT MODE

Programmable

Width and Polarity

Analog

Video In

P

1

P

2

P

3

P

4

P

5

P

6

P

7

P

8

P

0

P

9

HS

OUT

P

10

P

11

The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.

The sampling phase setting determines its relative position to the rest of the AFE’s output signals

DATACLK

HSYNC

IN

D

0

R

D

2

D

1

R

t

FIGURE 6. 48 BIT OUTPUT MODE, INTERLEAVED TIMING

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