1

®

FN8218.3

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X98017

170MHz Triple Video Digitizer with

Digital PLL

The X98017 3-channel, 8-bit Analog Front End (AFE)

contains all the components necessary to digitize analog

RGB or YUV graphics signals from personal computers,

workstations and video set-top boxes. The fully differential

analog design provides high PSRR and dynamic

performance to meet the stringent requirements of the

graphics display industry. The AFE’s 170MSPS conversion

rate supports resolutions up to UXGA at 60Hz refresh rate,

while the front end's high input bandwidth ensures sharp

images at the highest resolutions.

To minimize noise, the X98017's analog section features 2

sets of pseudo-differential RGB inputs with programmable

input bandwidth, as well as internal DC restore clamping

(including mid-scale clamping for YUV signals). This is

followed by the programmable gain/offset stage and the

three 170MSPS Analog-to-Digital Converters (ADCs).

Automatic Black Level Compensation (ABLC™

) eliminates

part-to-part offset variation, ensuring perfect black level

performance in every application.

The X98017's digital PLL generates a pixel clock from the

analog source's HSYNC or SOG (Sync-On-Green) signals.

Pixel clock output frequencies range from 10MHz to 170MHz

with sampling clock jitter of 250ps peak to peak.

Features

• 170MSPS maximum conversion rate

• Low PLL clock jitter (250ps p-p @ 170MSPS)

• 64 interpixel sampling positions

• Programmable bandwidth (100MHz to 780MHz)

• 2 channel input multiplexer

• RGB and YUV 4:2:2 output formats

• 5 embedded voltage regulators allow operation from

single 3.3V supply and enhance performance, isolation

• Completely independent 8 bit gain/10 bit offset control

• CSYNC and SOG support

• Trilevel sync detection

• Pb-free plus anneal available (RoHS compliant)

Applications

• LCD Monitors and Projectors

• Digital TVs

• Plasma Display Panels

• RGB Graphics Processing

• Scan Converters

Simplified Block Diagram

PGA

8 bit ADC

Offset

DAC

ABLC™

8 or 16

x3

Sync

Processing

Digital PLL

Voltage

Clamp

3

3

AFE Configuration and Control

+

Data Sheet

March 8, 2006

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