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X9241AUV Datasheet(PDF) 3 Page - Intersil Corporation

Part # X9241AUV
Description  Quad Digital Controlled Potentionmeters (XDCP??
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

X9241AUV Datasheet(HTML) 3 Page - Intersil Corporation

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FN8164.5
December 14, 2006
Pin Descriptions
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9241A.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be wire-
ORed with any number of open drain or open collector
outputs. An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the guidelines
for calculating typical values on the bus pull-up resistors
graph.
Address
The Address inputs are used to set the least significant 4 bits
of the 8-bit slave address. A match in the slave address
serial data stream must be made with the Address input in
order to initiate communication with the X9241A.
Potentiometer Pins
VH/RH(VH0/RH0—VH3/RH3), VL/RL (VL0/RL0—VL3/RL3)
The RH and RL inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
VW/RW (VW0/RW0—VW3/RW3)
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
Pin Configuration
X9241AUP
X9241AUP
5 ±10%
50
0 to +70
20 Ld PDIP
X9241AUPZ (Note)
X9241AUP Z
0 to +70
20 Ld PDIP*** (Pb-free)
X9241AUPI
X9241AUPI
-40 to +85
20 Ld PDIP
X9241AUPIZ (Note)
X9241AUPI Z
-40 to +85
20 Ld PDIP*** (Pb-free)
X9241AUS*, **
X9241AUS
0 to +70
20 Ld SOIC
X9241AUSZ* (Note)
X9241AUS Z
0 to +70
20 Ld SOIC (Pb-free)
X9241AUSI*, **
X9241AUSI
-40 to +85
20 Ld SOIC
X9241AUSIZ* (Note)
X9241AUSI Z
-40 to +85
20 Ld SOIC (Pb-free)
X9241AUV*
X9241AUV
0 to +70
20 Ld TSSOP
X9241AUVZ* (Note)
X9241AUV Z
0 to +70
20 Ld TSSOP (Pb-free)
X9241AUVI*, **
X9241AUVI
-40 to +85
20 Ld TSSOP
X9241AUVIZ* (Note)
X9241AUVI Z
-40 to +85
20 Ld TSSOP (Pb-free)
*Add "T1" suffix for tape and reel.
**Add “T2” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
***Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Ordering Information (Continued)
PART NUMBER
PART MARKING
VCC LIMITS
(V)
POTENTIOMETER
ORGANIZATION
(k)
TEMP RANGE
(°C)
PACKAGE
Pin Names
SYMBOL
DESCRIPTION
SCL
Serial Clock
SDA
Serial Data
A0–A3
Address
VH0/RH0–VH3/RH3,
VL0/RL0–VL3/RL3
Potentiometer Pins (terminal equivalent)
VW0/RW0–VW3/RW3
Potentiometer Pins (wiper equivalent)
VW0/RW0
A0
A2
VH1/RH1
SDA
VSS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
A1
A3
SCL
DIP/SOIC/TSSOP
X9241A
VL0/RL0
VH0/RH0
VW1/RW1
VL1/RL1
VW3/RW3
VL3/RL3
VH3/RH3
VW2/RW2
VL2/RL2
VH2/RH2
X9241A
Pot 0 = 50k
Pot 1 = 50k
Pot 2 = 50k
Pot 3 = 50k


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