Electronic Components Datasheet Search |
|
X5043M8-2.7 Datasheet(PDF) 8 Page - Intersil Corporation |
|
X5043M8-2.7 Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 21 page 8 FN8126.2 March 16, 2006 SPI Serial Memory The memory portion of the device is a CMOS Serial EEPROM array with Intersil’s block lock protection. The array is internally organized as 512 x 8 bits. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Intersil’s proprietary Direct Write™ cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. The device contains an 8-bit instruction register that controls the operation of the device. The instruction code is written to the device via the SI input. There are two write operations that requires only the instruction byte. There are two read operations that use the instruction byte to initiate the output of data. The remainder of the operations require an instruction byte, an 8-bit address, then data bytes. All instruction, address and data bits are clocked by the SCK input. All instructions (Table 1), addresses and data are transferred MSB first. Clock and Data Timing Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. CS must be LOW during the entire operation. Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first. VTRIP Programming Apply 5V to VCC Decrement VCC RESET pin goes active? Measured VTRIP -Desired VTRIP DONE Execute Sequence Reset VTRIP Set VCC = VCC Applied = Desired VTRIP Execute Sequence Set VTRIP New VCC Applied Old VCC Applied (VCC = VCC–10mV) Execute Sequence Reset VTRIP Error ≤ -Emax -Emax < Error < Emax YES NO Error ≥ Emax Emax = Maximum Desired Error - Error = New VCC Applied Old VCC Applied - Error = FIGURE 4. VTRIP PROGRAMMING SEQUENCE TABLE 1. INSTRUCTION SET INSTRUCTION NAME INSTRUCTION FORMAT* OPERATION WREN 0000 0110 Set the Write Enable Latch (Enable Write Operations) WRDI 0000 0100 Reset the Write Enable Latch (Disable Write Operations) RSDR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register (Watchdog and Block Lock) READ 0000 A8011 Read Data from Memory Array Beginning at Selected Address WRITE 0000 A8010 Write Data to Memory Array Beginning at Selected Address (1 to 16 bytes) X5043, X5045 |
Similar Part No. - X5043M8-2.7 |
|
Similar Description - X5043M8-2.7 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |