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X95840UV20IZ-2.7 Datasheet(PDF) 5 Page - Intersil Corporation |
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X95840UV20IZ-2.7 Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 13 page 5 FN8213.2 July 5, 2006 SDA vs SCL Timing tSU:DAT Input Data Setup Time From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC 100 ns tHD:DAT Input Data Hold Time From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window. 0ns tSU:STO STOP Condition Setup Time From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC. 600 ns tHD:STO STOP Condition Setup Time From SDA rising edge to SCL falling edge. Both crossing 70% of VCC. 600 ns tDH (Note 15) Output Data Hold Time From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window. 0ns tR (Note 15) SDA and SCL Rise Time From 30% to 70% of VCC 20 + 0.1 * Cb 250 ns tF (Note 15) SDA and SCL Fall Time From 70% to 30% of VCC 20 + 0.1 * Cb 250 ns Cb (Note 15) Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF Rpu (Note 15) SDA and SCL Bus Pull-up Resistor Off-chip Maximum is determined by tR and tF. For Cb = 400pF, max is about 2~2.5k Ω. For Cb = 40pF, max is about 15~20k Ω 1k Ω tWP (Notes 15, 16) Non-volatile Write Cycle Time 12 20 ms tSU:WPA A2, A1, A0, and WP Setup Time Before START condition 600 ns tHD:WPA A2, A1, A0, and WP Hold Time After STOP condition 600 ns Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP (Note 1) MAX UNITS tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DAT SCL SDA (INPUT TIMING) SDA (OUTPUT TIMING) tF tLOW tBUF tAA tR X95840 |
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