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X95820 Datasheet(PDF) 10 Page - Intersil Corporation |
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X95820 Datasheet(HTML) 10 Page - Intersil Corporation |
10 / 12 page 10 FN8212.2 July 18, 2006 All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The X95820 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (See Figure 15). A START condition is ignored during the power up sequence and during internal non-volatile write cycles. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (See Figure 15). A STOP condition at the end of a read operation, or at the end of a write operation to volatile bytes only places the device in its standby mode. A STOP condition during a write operation to a non-volatile byte, initiates an internal non-volatile write cycle. The device enters its standby state when the internal non-volatile write cycle is completed. An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 16). The X95820 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The X95820 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation A valid Identification Byte contains 1010 as the four MSBs, and the following three bits matching the logic values present at pins A2, A1, and A0. The LSB in the Read/Write bit. Its value is “1” for a Read operation, and “0” for a Write operation (See Table 2). TABLE 2. IDENTIFICATION BYTE FORMAT 1 0 1 0 A2 A1 A0 R/W (MSB) (LSB) Logic values at pins A2, A1, and A0 respectively SDA SCL START DATA DATA STOP STABLE CHANGE DATA STABLE FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS SDA Output from Transmitter SDA Output from Receiver 8 1 9 START ACK SCL from Master High Impedance High Impedance FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER S t a r t S t o p Identification Byte Address Byte Data Byte A C K Signals from the Master Signals from the X95820 A C K 1 0 1 00 A C K Write Signal at SDA 00 0 0 A2A1A0 FIGURE 17. BYTE WRITE SEQUENCE X95820 |
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