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X9525 Datasheet(PDF) 4 Page - Intersil Corporation |
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X9525 Datasheet(HTML) 4 Page - Intersil Corporation |
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4 / 24 page  4 FN8210.1 January 3, 2006 minate further data transmissions if an ACKNOWLEDGE is not detected. The master must then issue a STOP condition to place the device into a known state. DEVICE INTERNAL ADDRESSING Addressing Protocol Overview The user addressable internal components of the X9525 can be split up into three main parts: —Two Digitally Controlled Potentiometers (DCPs) —EEPROM array —Control and Status (CONSTAT) Register Depending upon the operation to be performed on each of these individual parts, a 1, 2 or 3 Byte proto- col is used. All operations however must begin with the Slave Address Byte being issued on the SDA pin. The Slave address selects the part of the X9525 to be addressed, and specifies if a Read or Write opera- tion is to be performed. It should be noted that in order to perform a write opera- tion to either a DCP or the EEPROM array, the Write Enable Latch (WEL) bit must first be set (See “BL1, BL0: Block Lock protection bits - (Nonvolatile)” on page 12.) Slave Address Byte Following a START condition, the master must output a Slave Address Byte (Refer to Figure 4.). This byte con- sists of four parts: —The Device Type Identifier which consists of the most significant four bits of the Slave Address (SA7 - SA4). The Device Type Identifier must always be set to 1010 in order to select the X9525. —SA3 is the Physical Device Address bit, whose logic level must match that of the corresponding A0 pin in order to enable communication to the X9525. —The next two bits (SA2 - SA1) are the Internal Device Address bits. Setting these bits to 00 internally selects the EEPROM array, while setting these bits to 11 selects the DCP structures in the X9525. The CON- STAT Register may be selected using the Internal Device Address 10. —The Least Significant Bit of the Slave Address (SA0) Byte is the R/W bit. This bit defines the operation to be performed on the device being addressed (as defined in the bits SA2 - SA1). When the R/W bit is “1”, then a READ operation is selected. A “0” selects a WRITE operation (Refer to Figure 4.) SCL from Master Data Output from Transmitter Data Output from Receiver 8 1 9 Start Acknowledge Figure 3. Acknowledge Response From Receiver SCL from Master SA6 SA7 SA5 SA3 SA2 SA1 SA0 DEVICE TYPE IDENTIFIER READ / SA4 Internal Address (SA2 - SA1) Internally Addressed Device 00 EEPROM Array 10 CONSTAT Register 11 DCP Bit SA0 Operation 0WRITE 1 READ R/ W Figure 4. Slave Address Format 101 0 WRITE ADDRESS INTERNAL DEVICE A0 ADDRESS PHYSICAL DEVICE X9525 |
Similar Part No. - X9525_06 |
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Similar Description - X9525_06 |
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