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X9523 Datasheet(PDF) 6 Page - Intersil Corporation

Part No. X9523
Description  Laser Diode Control for Fiber Optic Modules
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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X9523 Datasheet(HTML) 6 Page - Intersil Corporation

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6
FN8209.1
January 3, 2006
final STOP condition), the X9523 initiates an internal high
voltage write cycle. This cycle typically requires 5 ms.
During this time, no further Read or Write commands can
be issued to the device. Write Acknowledge Polling is
used to determine when this high voltage write cycle has
been completed.
To perform acknowledge polling, the master issues a
START condition followed by a Slave Address Byte. The
Slave Address issued must contain a valid Internal
Device Address. The LSB of the Slave Address (R/W)
can be set to either 1 or 0 in this case. If the device is still
busy
with
the
high
voltage
cycle
then
no
ACKNOWLEDGE will be returned. If the device has
completed the write operation, an ACKNOWLEDGE will
be returned and the host can then proceed with a read or
write operation. (Refer to Figure 5.).
DIGITALLY CONTROLLED POTENTIOMETERS
DCP Functionality
The X9523 includes two independent resistor arrays.
These arrays respectively contain 99 and 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (RHx and RLx
inputs - where x = 1,2).
At both ends of each array and between each resistor
segment there is a CMOS switch connected to the wiper
(Rwx) output. Within each individual array, only one
switch may be turned on at any one time. These
switches are controlled by the Wiper Counter Register
(WCR) (See Figure 6). The WCR is a volatile register.
On power-up of the X9523, wiper position data is auto-
matically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The Table below
shows the Initial Values of the DCP WCR’s before the
contents of the NVM is loaded into the WCR.
ACK
returned?
Issue Slave Address
Byte (Read or Write)
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue STOP
Issue START
NO
YES
High Voltage Cycle
complete. Continue
command sequence?
Issue STOP
NO
Continue normal
Read or Write
command sequence
PROCEED
YES
Figure 5.
Acknowledge Polling Sequence
DECODER
RESISTOR
ARRAY
RHx
FET
SWITCHES
RLx
RWx
0
1
2
N
WIPER
REGISTER
COUNTER
NON
MEMORY
VOLATILE
(WCR)
(NVM)
“WIPER”
Figure 6.
DCP Internal Structure
DCP
Initial Values Before Recall
R1 / 100 TAP
VL / TAP = 0
R2 / 256 TAP
VH / TAP = 255
X9523


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