 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
X9523 Datasheet(PDF) 3 Page - Intersil Corporation |
|
||||||||||||||||||||||||||||||
X9523 Datasheet(HTML) 3 Page - Intersil Corporation |
|
|
3 / 28 page 
3 FN8209.1 January 3, 2006 PIN ASSIGNMENT Pin Name Function 1 RH2 Connection to end of resistor array for (the 256 Tap) DCP 2. 2 Rw2 Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2. 3 RL2 Connection to other end of resistor array for (the 256 Tap) DCP 2. 4V3 V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When the V3 input is higher than the VTRIP3 threshold voltage, V3RO makes a transition to a HIGH level. Connect V3 to VSS when not used. 5V3RO V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is greater than VTRIP3 and goes LOW when V3 is less than VTRIP3. There is no delay circuitry on this pin. The V3RO pin requires the use of an external “pull-up” resistor. 6MR Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the V1RO pin (V1/Vcc RESET Output pin). V1RO will remain HIGH for time tpurst after MR has returned to it’s normally LOW state. The reset time can be selected using bits POR1 and POR0 in the CONSTAT Register. The MR pin requires the use of an external “pull-down” resistor. 7WP Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and the device DCP Write Lock feature is active (i.e. the DCP Write Lock bit is “1”), then no “write” (volatile or nonvolatile) operations can be performedon the wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” re- sistor, thus if left floating the write protection feature is disabled. 8SCL Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input and output. 9SDA Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA pin input buffer is always active (not gated). This pin requires an external pull up re- sistor. 10 Vss Ground. 11 RL1 Connection to other end of resistor for (the 100 Tap) DCP 1. 12 Rw1 Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1. 13 RH1 Connection to end of resistor array for (the 100 Tap) DCP 1. 17 V2 V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When the V2 input is greater than the VTRIP2 threshold voltage, V2RO makes a transition to a HIGH level. Connect V2 to VSS when not used. 18 V2RO V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is greater than VTRIP2, and goes LOW when V2 is less than VTRIP2. There is no power-up reset delay circuitry on this pin. The V2RO pin requires the use of an external “pull-up” resistor. 19 V1RO V1 / Vcc RESET Output. This is an active HIGH, open drain output which becomes active whenever V1 / Vcc falls below VTRIP1. V1RO becomes active on power-up and remains active for a time tpurst after the power supply stabilizes (tpurst can be changed by varying the POR0 and POR1 bits of the internal control register). The V1RO pin requires the use of an external “pull-up” resistor. The V1RO pin can be forced active (HIGH) using the manual reset (MR) input pin. 20 V1 / Vcc Supply Voltage. 14, 15, 16, NC No Connect. X9523 |
English ▼
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
