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IRS2541STRPBF Datasheet(PDF) 8 Page - International Rectifier |
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IRS2541STRPBF Datasheet(HTML) 8 Page - International Rectifier |
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8 / 14 page  IRS254(0,1)(S)PbF www.irf.com Page 8 Watchdog Timer During an open circuit condition, without the watchdog timer, the HO output would remain high at all times and the charge stored in the bootstrap capacitor CBOOT would gradually discharge the floating power supply for the high-side driver, which would then be unable to fully switch on the upper MOSFET causing high losses. To maintain sufficient charge on the bootstrap capacitor, a watchdog timer has been implemented. In the condition where VIFB remains below VIFBTH, the HO output will be forced low after 20 µs and the LO output forced high. This toggling of the outputs will last for approximately 1 µs to maintain and replenish sufficient charge on CBOOT. Fig.4 Illustration of Watchdog Timer Bootstrap Capacitor and Diode The bootstrap capacitor value needs to be chosen so that it maintains sufficient charge for at least the approximately 20 µs interval until the watchdog timer allows the capacitor to recharge. If the capacitor value is too small, the charge will dissipate in less than 20 µs. The typical bootstrap capacitor is approximately 100 nF. The bootstrap diode should be a fast recovery or ultrafast recovery component to maintain good efficiency. Since the cathode of the bootstrap diode will be switching between zero and to the high voltage bus, the reverse recovery time of this diode is of critical importance. For additional information concerning the bootstrap components, refer to the Design Tip (DT 98-2), “Bootstrap Component Selection For Control ICs” at www.irf.com under Design Support Disable (ENN) Pin The disable pin can be used for dimming and open- circuit protection. When the ENN pin is held low, the chip remains in a fully functional state with no alterations to the operating environment. To disable the control feedback and regulation, a voltage greater than VENTH (approximately 2.5 V) needs to be applied to the ENN pin. With the chip in a disabled state, HO output will remain low, whereas the LO output will remain high to prevent VS from floating, in addition to maintaining charge on the bootstrap capacitor. The threshold for disabling the IRS254(0,1) has been set to 2.5 V to enhance immunity to any externally generated noise, or application ground noise. This 2.5 V threshold also makes it ideal to receive a drive signal from a local microcontroller. Dimming Mode To achieve dimming, a signal with constant frequency and set duty cycle can be fed into the ENN pin. There is a direct linear relationship between the average load current and duty cycle. If the ratio is 50%, 50% of the maximum set light output will be realized. Likewise if the ratio is 30%, 70% of the maximum set light output will be realized. A sufficiently high frequency of the dimming signal must be chosen to avoid flashing or “strobe light” effect. A signal on the order of a few kHz should be sufficient. The minimum amount of dimming achievable (light output approaches 0%) will be determined by the “on” time of the HO output, when in a fully functional regulating state. To maintain reliable dimming, it is recommended to keep the “off” time of the enable signal at least 10 times that of the HO “on” time. For example, if the application is running at 75 kHz with an input voltage of 100 V and an output voltage of 20 V, the HO “on” time will be 3.3 µs (one-fourth of the period – see calculations below) according to standard buck topology theory. This will set the minimum “off” time of the enable signal to 33 µs. s kHz HO V V V V Cycle Duty on in out µ 3 . 3 75 1 * % 20 % 20 100 * 100 20 100 time = = = = ∗ = HO LO |
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