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IRS2540SPBF Datasheet(PDF) 9 Page - International Rectifier |
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IRS2540SPBF Datasheet(HTML) 9 Page - International Rectifier |
9 / 14 page IRS254(0,1)(S)PbF www.irf.com Page 9 Enable Duty Cycle Relationship to Light Output 0 10 20 30 40 50 60 70 80 90 100 0 1020304050 60708090 100 Percentage of Light Output Fig.5 Light Output vs Enable Pin Duty Cycle Fig.6 IRS254(0,1) Dimming Signals Open Circuit Protection Mode By using the suggested voltage divider, capacitor, and zener diode, the output voltage can be clamped at any desired value. In open-circuit condition without output clamp, the positive output terminal will float at the high-side input voltage. Switching will still occur between the HO and LO outputs, whether due to the output voltage clamp or the watchdog timer. Transients and switching will be observed at the positive output terminal as seen in Fig. 8. The difference in signal shape, between the output voltage and the IFB, is due to the capacitor used to form the voltage clamp. The repetition of the spikes can be reduced by simply increasing the capacitor size. The two resistors form a voltage divider for the output, which is then fed into the cathode of the zener diode. The diode will only conduct, flooding the enable pin, when its nominal voltage is exceeded. The chip will enter a disabled state once the divider network produces a voltage at least 2.5 V greater than the zener rating. The capacitor serves only to filter and slow the transients/switching at the positive output terminal. The clamped output voltage can be determined by the following analysis. The choice of capacitor is at the designer’s discretion. ( )( ) Voltage Rated Nominal Diode Zener 5 . 2 2 2 1 = + + = DZ R R R DZ V V out Fig.8 Open Circuit Fault Signals, with Clamp Under-voltage Lock-out Mode The under-voltage lock-out mode (UVLO) is defined as the state IRS254(0,1) is in when VCC is below the turn-on threshold of the IC. During startup conditions, if the IC supply remains below VCCUV+, the IRS254(0,1) will enter the UVLO mode. This state is very similar to when the IC has been disabled via control signals, except that LO is also held low. When the supply is increased to VCCUV+, the IC enters the normal operation mode. If already in normal Fig.7 Open Circuit Protection Scheme 3 4 EN IFB Vout R1 R2 HO LO EN |
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