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X5001PZ-2.7A Datasheet(PDF) 8 Page - Intersil Corporation

Part # X5001PZ-2.7A
Description  CPU Supervisor
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

X5001PZ-2.7A Datasheet(HTML) 8 Page - Intersil Corporation

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8
FN8125.1
May 30, 2006
Watchdog Timer Register
Watchdog Timer Control Bits
The watchdog timer control bits, WD0 and WD1,
select the watchdog time out period. These nonvola-
tile bits are programmed with the set watchdog timer
(SWDT) instruction.
Write Watchdog Register Operation
Changing the watchdog timer register is a two step
process. First, the change must be enabled by setting
the watchdog change latch (see below). This instruc-
tion is followed by the set watchdog timer (SWDT)
instruction, which includes the data to be written (Fig-
ure 5). Data bits 3 and 4 contain the watchdog settings
and data bits 0, 1, 2, 5, 6 and 7 must be “0”.
Watchdog Change Latch
The watchdog change latch must be SET before a
Write watchdog timer operation is initiated. The
Enable Watchdog Change (EWDC) instruction will set
the latch and the Disable Watchdog Change (DWDC)
instruction will reset the latch (Figure 6). This latch is
automatically reset upon a power-up condition and
after the completion of a valid nonvolatile write cycle.
Read Watchdog Timer Register Operation
If there is not a nonvolatile write in progress, the read
watchdog timer instruction returns the setting of the
watchdog timer control bits. The other bits are
reserved and will return’0’ when read. See Figure 3.
If a nonvolatile write is in progress, the read watchdog
timer register Instruction returns a HIGH on SO. When
the nonvolatile write cycle is completed, a separate read
watchdog timer instruction should be used to determine
the current status of the watchdog control bits.
RESET Operation
The RESET (X5001) output is designed to go LOW
whenever VCC has dropped below the minimum trip
point and/or the watchdog timer has reached its pro-
grammable time out limit.
The RESET output is an open drain output and
requires a pull-up resistor.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
– The watchdog change latch is reset.
– The RESET signal is active for tPURST.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– A EWDC instruction must be issued to enable a
change to the watchdog timeout setting.
–CS must come HIGH at the proper clock count in
order to implement the requested changes to the
watchdog timeout setting.
Table 1. Instruction Set Definition
Note:
Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.
765
4321
0
00
0
WD1 WD0
00
0
Watchdog Control Bits
Watchdog Time Out
(Typical)
WD1
WD0
0
0
1.4 seconds
0
1
600 milliseconds
1
0
200 milliseconds
1
1
disabled
Instruction Format
Instruction Name and Operation
0000 0110
EWDC: Enable Watchdog Change Operation
0000 0100
DWDC: Disable Watchdog Change Operation
0000 0001
SWDT: Set Watchdog Timer control bits:
Instruction followed by contents of register: 000(WD1) (WD0)000
See Watchdog Timer Settings and Figure 7.
0000 0101
RWDT: Read Watchdog Timer Control Bits
X5001


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