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X40420V14-B Datasheet(PDF) 5 Page - Intersil Corporation |
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X40420V14-B Datasheet(HTML) 5 Page - Intersil Corporation |
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5 / 25 page  5 May 25, 2006 PRINCIPLES OF OPERATION Power-on Reset Applying power to the X40420, X40421 activates a Power-on Reset Circuit that pulls the RESET/RESET pins active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. – It prevents the processor from operating prior to sta- bilization of the oscillator. – It allows time for an FPGA to download its configura- tion prior to initialization of the circuit. – It prevents communication to the EEPROM, greatly reducing the likelihood of data corruption on power-up. When VCC exceeds the device VTRIP1 threshold value for tPURST (selectable) the circuit releases the RESET (X40421) and RESET (X40420) pin allowing the system to begin operation. Figure 1. Connecting a Manual Reset Push-Button Manual Reset By connecting a push-button directly from MR to ground, the designer adds manual system reset capa- bility. The MR pin is LOW while the push-button is closed and RESET/RESET pin remains LOW for tPURST or till the push-button is released and for tPURST thereafter. A weak pull up resistor is connected to the MR pin. Low Voltage V1 Monitoring During operation, the X40420, X40421 monitors the VCC level and asserts RESET if supply voltage falls below a preset minimum VTRIP1. The RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The V1FAIL signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP1 for tPURST. Low Voltage V2 Monitoring The X40420, X40421 also monitors a second voltage level and asserts V2FAIL if the voltage falls below a pre- set minimum VTRIP2. The V2FAIL signal is either ORed with RESET to prevent the microprocessor from operat- ing in a power fail or brownout condition or used to inter- rupt the microprocessor with notification of an impending power failure. The V2FAIL signal remains active until the VCC drops below 1V (VCC falling). It also remains active until V2MON returns and exceeds VTRIP2. V2MON voltage monitor is powered by VOUT. If VCC and VBATT go away, V2MON cannot be monitored. Figure 2. Two Uses of Multiple Voltage Monitoring WATCHDOG TIMER The Watchdog Timer circuit monitors the microproces- sor activity by monitoring the SDA and SCL pins. A standard read or write sequence to any slave address byte restarts the watchdog timer and prevents the WDO signal to go active. A minimum sequence to reset the watchdog timer requires four microprocessor instructions namely, a Start, Clock Low, Clock High and Stop. The state of two nonvolatile control bits in the Status Register determine the watchdog timer period. The microprocessor can change these watch- dog bits by writing to the X40420, X40421 control reg- ister. MR System Reset Manual Reset X40420, X40421 RESET Unreg. Supply VCC 5V Reg V2MON X40420 Resistors selected so 3V appears on V2MON when unregulated supply reaches 6V. Unreg. Supply VCC X40421 RESET V2FAIL System VOUT Reset RESET V2FAIL VOUT System Reset Notice: No external components required to monitor two voltages. R R V2MON 5V Reg 3V Reg X40420, X40421 |
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Similar Description - X40420V14-B |
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