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X1226V8I Datasheet(PDF) 8 Page - Intersil Corporation |
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X1226V8I Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 25 page 8 FN8098.3 May 8, 2006 WEL: Write Enable Latch—Volatile The WEL bit controls the access to the CCR and mem- ory array during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to the CCR or any array address will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the Status Register. Once set, WEL remains set until either reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the Status Register) or until the part powers up again. Writes to WEL bit do not cause a nonvolatile write cycle, so the device is ready for the next operation immediately after the stop condition. RTCF: Real Time Clock Fail Bit—Volatile This bit is set to a “1” after a total power failure. This is a read only bit that is set by hardware (X1226 inter- nally) when the device powers up after having lost all power to the device (both VCC and VBACK go to 0V). The bit is set regardless of whether VCC or VBACK is applied first. The loss of only one of the supplies does not set the RTCF bit to “1”. On power-up after a total power failure, all registers are set to their default states and the clock will not increment until at least one byte is written to the clock register. The first valid write to the RTC section after a complete power failure resets the RTCF bit to “0” (writing one byte is suffi- cient). Unused Bits: This device does not use bits 3 or 4 in the SR, but must have a zero in these bit positions. The Data Byte output during a SR read will contain zeros in these bit locations. CONTROL REGISTERS The Control Bits and Registers, described under this section, are nonvolatile. Block Protect Bits—BP2, BP1, BP0 The Block Protect Bits, BP2, BP1 and BP0, determine which blocks of the array are write protected. A write to a protected block of memory is ignored. The block protect bits will prevent write operations to one of eight segments of the array. The partitions are described in Table 3. INTERRUPT CONTROL AND FREQUENCY OUTPUT REGISTER (INT) Interrupt Control and Status Bits (IM, AL1E, AL0E) There are two Interrupt Control bits, Alarm 1 Interrupt Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to specifically enable or disable the alarm interrupt signal output (IRQ). The interrupts are enabled when either the AL1E and AL0E bits are set to ‘1’, respectively. Table 3. Block Protect Bits Two volatile bits (AL1 and AL0), associated with the two alarms respectively, indicate if an alarm has happened. These bits are set on an alarm condition regardless of whether the IRQ interrupt is enabled. The AL1 and AL0 bits in the status register are reset by the falling edge of the eighth clock of a read of the register containing the bits. Pulse Interrupt Mode The pulsed interrrupt mode allows for repetitive or recurring alarm functionality. Hence an repetitive or recurring alarm can be set for every nth second, or nth minute, or nth hour, or nth date, or for the same day of the week. The pulsed interrupt mode can be consid- ered a repetitive interrupt mode, with the repetition rate set by the time setting fo the alarm. The Pulse Interrupt Mode is enabled when the IM bit is set. The Alarm IRQ output will output a single pulse of short duration (approximately 10-40ms) once the alarm condition is met. If the interrupt mode bit (IM bit) is set, then this pulse will be periodic. Protected Addresses X1226 Array Lock 0 0 0 None None 0 0 1 6000h – 7FFFh Upper 1/4 0 1 0 4000h – 7FFFh Upper 1/2 0 1 1 0000h – 7FFFh Full Array 1 0 0 0000h – 007Fh First Page 1 0 1 0000h – 00FFh First 2 pgs 1 1 0 0000h – 01FFh First 4 pgs 1 1 1 0000h – 03FFh First 8 Pgs IM Bit Interrupt/Alarm Frequency 0 Single Time Event Set By Alarm 1 Repetitive/Recurring Time Event Set By Alarm X1226 |
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