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OM5232 Datasheet(PDF) 3 Page - NXP Semiconductors

Part No. OM5232
Description  CMOS single-chip 8-bit microcontroller
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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OM5232 Datasheet(HTML) 3 Page - NXP Semiconductors

 
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Philips Semiconductors
Product specification
OM5232
CMOS single-chip 8-bit microcontroller
December 1994
3
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC
DIP
QFP
TYPE
NAME AND FUNCTION
VSS
20
6, 16,
28, 39
I
Ground: 0V reference. With the QFP package all VSS pins (VSS1 to VSS4) must be connected.
VDD
40
38
I
Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
P0.0–0.7
39–32
37–30
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them
float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address
and data bus during accesses to external program and data memory. In this application, it uses
strong internal pull-ups when emitting 1s.
P1.0–P1.5
1–6
40–44,
1
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7 which
are open drain. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current
because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Alternate functions
include:
P1.6
7
2
I/O
open drain output
P1.7
8
3
I/O
open drain output
P2.0–P2.7
21–28
18–25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port
2 pins that are externally being pulled low will source current because of the internal pull-ups.
(See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to external data memory that use 16-bit
addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s.
During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the
contents of the P2 special function register.
P3.0–P3.7
10–17
5,
7–13
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port
3 pins that are externally being pulled low will source current because of the pull-ups. (See DC
Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as
listed below:
10
5
I
RxD (P3.0): Serial input port
11
7
O
TxD (P3.1): Serial output port
12
8
I
INT0 (P3.2): External interrupt
13
9
I
INT1 (P3.3): External interrupt
14
10
I
T0 (P3.4): Timer 0 external input
15
11
I
T1 (P3.5): Timer 1 external input
16
12
O
WR (P3.6): External data memory write strobe
17
13
O
RD (P3.7): External data memory read strobe
RST
9
4
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device.
An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to
VDD.
ALE
30
27
I/O
Address Latch Enable: Output pulse for latching the low byte of the address during an access
to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator
frequency. Note that one ALE pulse is skipped during each access to external data memory.
PSEN
29
26
O
Program Store Enable: Read strobe to external program memory via Port 0 and Port 2. It is
activated twice each machine cycle during fetches from the external program memory. When
executing out of external program memory two activations of PSEN are skipped during each
access to external data memory. PSEN is not activated (remains HIGH) during no fetches from
external program memory. PSEN can sink/source 8 LSTTL inputs and can drive CMOS inputs
without external pull–ups.
EA
31
29
I
External Access: If during a RESET, EA is held at TTL, level HIGH, the CPU executes out of the
internal program memory ROM provided the Program Counter is less than 16384. If during a
RESET, EA is held a TTL LOW level, the CPU executes out of external program memory. EA is
not allowed to float.
XTAL1
19
15
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
XTAL2
18
14
O
Crystal 2: Output from the inverting oscillator amplifier.
NOTE:
To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VDD + 0.5V or VSS – 0.5V, respectively.


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