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OM5232 Datasheet(PDF) 5 Page - NXP Semiconductors

Part No. OM5232
Description  CMOS single-chip 8-bit microcontroller
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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OM5232 Datasheet(HTML) 5 Page - NXP Semiconductors

 
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Philips Semiconductors
Product specification
OM5232
CMOS single-chip 8-bit microcontroller
December 1994
5
ROM CODE PROTECTION
The OM5232 has an additional security feature. ROM code
protection may be selected by setting a mask–programmable
security bit (i.e., user dependent). This feature may be requested
during ROM code submission. When selected, the ROM code is
protected and cannot be read out at any time by any test mode or by
any instruction in the external program memory space.
The MOVC instructions are the only instructions that have access to
program code in the internal or external program memory. The EA
input is latched during RESET and is “don’t care” after RESET
(also if the security bit is not set). This implementation prevents
reading internal program code by switching from external program
memory to internal program memory during a MOVC instruction or
any other instruction that uses immediate data.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol, page 2.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
Reset
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
VDD and RST must come up at the same time for a proper start-up.
Idle Mode
In the idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset.
Power-Down Mode
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. The control
bits for the reduced power modes are in the special function register
PCON. Table 2 shows the state of the I/O ports during low current
operating modes.
Table 2.
External Pin Status During Idle and Power-Down Mode
MODE
PROGRAM
MEMORY
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
Idle
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power-down
Internal
0
0
Data
Data
Data
Data
Power-down
External
0
0
Float
Data
Data
Data
Serial Control Register (S1CON) – See Table 3
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
S1CON (D8H)
Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.
Table 3.
Serial Clock Rates
BIT FREQUENCY (kHz) AT fOSC
CR2
CR1
CR0
6MHz
12MHz
16MHz
fOSC DIVIDED BY
0
0
0
23
47
62.5
256
0
0
1
27
54
71
224
0
1
0
31.25
62.5
83.3
192
0
1
1
37
75
100
160
1
0
0
6.25
12.5
17
960
1
0
1
50
100
133
120
1
1
0
100
200
267
60
1
1
1
0.24 < 62.5
0 to 255
0.49 < 62.5
0 to 254
0.65 < 55.6
0 to 253
96
× (256 – (reload value Timer 1))
reload value range Timer 1 (in mode 2)


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