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OM4068 Datasheet(PDF) 9 Page - NXP Semiconductors |
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OM4068 Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 28 page 1998 Jun 18 9 Philips Semiconductors Product specification LCD driver for low multiplex rates OM4068 Power-on reset The on-chip power-on reset block initializes the chip after power-on or power failures. The OM4068 resets to a starting condition as follows: • All backplane and segment outputs are set to VSS (display off) • All shift registers and latches are set in 3-state • SDOUT (allowing serial cascading) is set to logic 0 (with SCE LOW) • Power-down mode. Data transfers on the serial bus should be avoided for 0.5 ms following power-on to allow completion of the reset action. Power-down After power-on the chip is in power-down mode as long as the serial clock is not active. During power-down all static currents are switched off (no internal oscillator, no timing and no bias level generation) and all LCD-outputs are 3-stated. The power-on reset functions remain enabled. The power-down mode is disabled at the first rising edge of the serial clock SCLK. LCD bias voltage generator The intermediate bias voltages for the LCD display are generated on-chip. This removes the need for an external resistive bias chain and significantly reduces the system power consumption. The full-scale LCD voltage VOP equals VLCD − VSS. The optimum value of VOP depends on the LCD threshold voltage (Vth) and the number of bias levels. Fractional LCD biasing voltages are obtained from an internal voltage divider of three series resistors (1 ⁄3bias) connected between VLCD and VSS. The centre resistor can be switched out of the circuit to provide a 1 ⁄2bias voltage level for the 1 : 2 multiplex configuration. The bias levels depend on the multiplex rate and are selected automatically when the display configuration is selected using M1 and M0. LCD voltage selector The LCD voltage selector (control logic) coordinates the multiplexing of the LCD in accordance with the selected drive or display configuration. The operation of the voltage selector is controlled by the input pins M0 and M1 (see Table 2). Table 2 Drive mode selection For multiplex rates of 1 : 2 three bias levels are used including VLCD and VSS. Four bias level are used for the 1 : 3 multiplex rate. The various biasing configurations together with the biasing characteristics as functions of VOP =VLCD − VSS and the resulting discrimination ratios (D), are given in Table 3. A practical value for VOP is determinated by equating Voff(rms) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10% contrast. In static mode a suitable choice is VOP >3Vth. M1 M0 DRIVE MODE 0 0 test mode (not user accessible) 0 1 static drive (1 : 1) 1 0 duplex drive (1 : 2) 1 1 triplex drive (1 : 3) |
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