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ISL12021 Datasheet(PDF) 16 Page - Intersil Corporation |
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ISL12021 Datasheet(HTML) 16 Page - Intersil Corporation |
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16 / 24 page  16 FN6451.0 March 30, 2007 GAIN FACTOR OF ATR BIT (BETA)<3:0> Beta is specified to take care of the Cm variations of the crystal. Most crystals specify Cm around 2.2fF. For example, if Cm > 2.2fF, the actual ATR steps may reduce from 1ppm/step to approximately 0.80ppm/step. Beta is then used to adjust for this variation and restore the step size to 1ppm/step. The value for BETA should only be changed while the TSE (Temp Sense Enable) bit is “0”. The procedure for writing the BETA register involves two steps. First, Write the new value of BETA with TSE = 0. Then Write the same value of BETA with TSE = 1. This will insure the next temp sense cycle will use the new BETA value. BETA values are limited in the range from 0100 to 1100 as shown in Table 16 . Final Analog Trimming Register (FATR) This register shows the final setting of ATR after temperature correction. It is read-only, the user cannot overwrite a value to this register. This value is accessible as a means of monitoring the temperature compensation function. See Table 17. Final Digital Trimming Register (FDTR) This Register shows the final setting of DTR after temperature correction. It is read-only, the user cannot overwrite a value to this register. The value is accessible as a means of monitoring the temperature compensation function. The corresponding clock adjustment values are shown in Table 19. The DTR setting is only positive as it is used to correct for the negative drift of a normal crystal over temperature. ALARM Registers (10h to 15h) The alarm register bytes are set up identical to the RTC register bytes, except that the MSB of each byte functions as an enable bit (enable = “1”). These enable bits specify which alarm registers (seconds, minutes, etc.) are used to make the comparison. Note that there is no alarm byte for year. The alarm function works as a comparison between the alarm registers and the RTC registers. As the RTC advances, the alarm will be triggered once a match occurs between the alarm registers and the RTC registers. Any one alarm register, multiple registers, or all registers can be enabled for a match. There are two alarm operation modes: Single Event and periodic Interrupt Mode: • Single Event Mode is enabled by setting the bit 7 on any of the Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to “0”, and disabling the frequency output. This mode permits a one-time match between the Alarm registers and the RTC registers. Once this match occurs, the ALM bit is set to “1” and the IRQ output will be pulled low and will remain low until the ALM bit is reset. This can be done manually or by using the auto-reset feature. • Interrupt Mode is enabled by setting the bit 7 on any of the Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to TABLE 15. FREQUENCY OF TEMPERATURE SENSING AND CORRECTION BIT BTSE BTSR TC PERIOD IN BATTERY MODE 00 OFF 01 OFF 1 0 10 Minutes 1 1 1 Minute TABLE 16. BETA VALUES BETA<3:0> ATR STEP ADJUSTMENT 0100 0.500 0101 0.625 0110 0.750 0111 0.875 1000 1.00 1001 1.125 1010 1.250 1011 1.375 1100 1.500 TABLE 17. FINAL ANALOG TRIMMING REGISTER ADDR 7 6 5 4 3 2 1 0 0Eh 0 0 FATR5 FATR4 FATR3 FATR2 FATR1 FATR0 TABLE 18. FINAL DIGITAL TRIMMING REGISTER ADDR 76543 2 1 0 0Fh FDTR2 FDTR1 FDTR0 TABLE 19. CLOCK ADJUSTMENT VALUES FOR FINAL DIGITAL TRIMMING REGISTER DTR<2:0> DECIMAL ppm ADJUSTMENT 000 0 0 001 1 32 010 2 64 011 3 96 100 4 128 101 5 160 110 6 196 111 7 -32 ISL12021 |
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