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NE567N Datasheet(PDF) 8 Page - NXP Semiconductors

Part # NE567N
Description  Tone decoder/phase-locked loop
Download  13 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

NE567N Datasheet(HTML) 8 Page - NXP Semiconductors

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Philips Semiconductors Linear Products
Product specification
NE/SE567
Tone decoder/phase-locked loop
April 15, 1992
410
Figure 3. Sensitivity Adjust
567
567
567
DECREASE
SENSITIVITY
INCREASE
SENSITIVITY
V+
R
R
1
1
1
SILICON
DIODES FOR
TEMPERATURE
COMPENSATION
(OPTIONAL)
2.5k
1.0k
50k
C3
C3
C3
RB
RC
V+
DECREASE
SENSITIVITY
INCREASE
SENSITIVITY
RA
connected to pin 6 without affecting the CCO duty cycle or
temperature stability.
OPERATING PRECAUTIONS
A brief review of the following precautions will help the user achieve
the high level of performance of which the 567 is capable.
1. Operation in the high input level mode (above 200mV) will free
the user from bandwidth variations due to changes in the in-band
signal amplitude. The input
stage is now limiting, however, so that out-band signals or high
noise levels can cause an apparent bandwidth reduction as the
inband signal is suppressed. Also, the limiting action will create
in-band components from sub-harmonic signals, so the 567
becomes sensitive to signals at fO/3, fO/5, etc.
2. The 567 will lock onto signals near (2n+1) fO, and will give an
output for signals near (4n+1) fO where n=0, 1, 2, etc. Thus,
signals at 5fO and 9fO can cause an unwanted output. If such
signals are anticipated, they should be attenuated before
reaching the 567 input.
3. Maximum immunity from noise and out-band signals is afforded
in the low input level (below 200mVRMS) and reduced bandwidth
operating mode. However, decreased loop damping causes the
worst-case lock-up time to increase, as shown by the Greatest
Number of Cycles Before Output vs Bandwidth graph.
4. Due to the high switching speeds (20ns) associated with 567
operation, care should be taken in lead routing. Lead lengths
should be kept to a minimum. The power supply should be
adequately bypassed close to the 567 with a 0.01
µF or greater
capacitor; grounding paths should be carefully chosen to avoid
ground loops and unwanted voltage variations. Another factor
which must be considered is the effect of load energization on
the power supply. For example, an incandescent lamp typically
draws 10 times rated current at turn-on. This can be somewhat
greater when the output stage is made less sensitive, rejection of
third harmonics or in-band harmonics (of lower frequency
signals) is also improved.
cause supply voltage fluctuations which could, for example, shift the
detection band of narrow-band systems sufficiently to cause
momentary loss of lock. The result is a low-frequency oscillation into
and out of lock. Such effects can be prevented by supplying heavy
load currents from a separate supply or increasing the supply filter
capacitor.
SPEED OF OPERATION
Minimum lock-up time is related to the natural frequency of the loop.
The lower it is, the longer becomes the turn-on transient. Thus,
maximum operating speed is obtained when C2 is at a minimum.
When the signal is first applied, the phase may be such as to initially
drive the controlled oscillator away from the incoming frequency
rather than toward it. Under this condition, which is of course
unpredictable, the lock-up transient is at its worst and the theoretical
minimum lock-up time is not achievable. We must simply wait for the
transient to die out.
The following expressions give the values of C2 and C3 which allow
highest operating speeds for various band center frequencies. The
minimum rate at which digital information may be detected without
information loss due to the turn-on transient or output chatter is
about 10 cycles per bit, corresponding to an information transfer rate
of fO/10 baud.
Rf
Figure 4. Chatter Prevention
567
V+
8
Cf
LOWER VALUE OF Cf
RL
Rf*
10k
*OPTIONAL - PERMITS
C3
567
V+
8
200 TO
RL
RA
C3
1
1k
10k
567
V+
8
1
10k
Rf
RL
V+
200 TO 1k
RA
1
Figure 5. Skew Adjust
567
567
567
V+
R
R
2
2
1
SILICON
DIODES FOR
TEMPERATURE
COMPENSATION
(OPTIONAL)
2.5k
1.0k
50k
C2
C2
C2
RB
RC
V+
RA
RAISES fO
LOWERS fO
RAISES fO
RAISES fO
LOWERS fO


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