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ISL65426 Datasheet(PDF) 19 Page  Intersil Corporation 

ISL65426 Datasheet(HTML) 19 Page  Intersil Corporation 
19 / 22 page 19 FN6340.2 February 21, 2007 The filter capacitor must have sufficiently low ESL and ESR so that ΔV < ΔVMAX. Most capacitor solutions rely on a mixture of high frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited highfrequency performance. Minimizing the ESL of the highfrequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation. The ESR of the bulk capacitors also creates the majority of the output voltage ripple. As the bulk capacitors sink and source the inductor AC ripple current, a voltage develops across the bulk capacitor VPPMAX. See Equation 5. The recommended load capacitance recommended is based on Equation 6. OUTPUT INDUCTOR SELECTION Once the output capacitors are selected, the maximum allowable ripple voltage, VPPMAX, determines the lower limit on the inductance. See Equation 7. Since the output capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductors must be capable of assuming the entire load current before the output voltage decreases more than ΔVMAX. This places an upper limit on inductance. Equation 8 gives the upper limit on output inductance for the cases when the trailing edge of the current transient causes the greater output voltage deviation than the leading edge. Equation 9 addresses the leading edge. Normally, the trailing edge dictates the inductance selection because duty cycles are usually less than 50%. Nevertheless, both inequalities should be evaluated, and inductance should be governed based on the lower of the two results. In each equation, L is the output inductance and C is the total output capacitance. The other concern when selecting an output inductor is the internally set current mode slope compensation. Designs should not allow inductor ripple currents below 0.125 times the maximum output current to prevent regulation issues. A good rule of thumb for selection of the output inductance value is 1/3 of the maximum load current for inductor ripple. The rule of thumb value, see Equation 10, with fall between the minimum inductance value calculated in Equation 7 and the maximum values determined from Equations 8 and 9. Input Capacitor Selection Input capacitors are responsible for sourcing the AC component of the input current flowing into the switching power devices. Their RMS current capacity must be sufficient to handle the AC component of the current drawn by the switching power devices which is related to duty cycle. The maximum RMS current required by the regulator is closely approximated by Equation 11. The important parameters to consider when selecting an input capacitor are the voltage rating and the RMS current rating. For reliable operation, select capacitors with voltage ratings above the maximum input voltage. Their voltage rating should be at least 1.25 times greater than the maximum input voltage, while a voltage rating of 1.5 times is a conservative guideline. The capacitor RMS current rating should be higher than the largest RMS current required by the circuit. Layout Considerations Careful printed circuit board (PCB) layout is critical in high frequency switching converter design. Current transitions from one device to another at this frequency induce voltage spikes across the interconnecting impedances and parasitic elements. These spikes degrade efficiency, lead to device overvoltage stress, radiate noise into sensitive nodes, and increase thermal stress on critical components. Careful component placement and PCB layout minimizes the voltage spikes in the converter. The following multilayer printed circuitry board layout strategies minimize the impact of board parasitics on converter performance and optimize the heatdissipating capabilities of the printed circuit board. This section highlights some important practices which should not be overlooked during the layout process. Figure 6 provides a top level view of the critical components, layer utilization, and signal routing for reference. ΔV ESL di dt  × ESR ΔI × [] + ≈ (EQ. 4) V PP MAX ESR V IN V OUT – ()V OUT Lf s × V IN ×  × = (EQ. 5) C OUT 0.5 I OUT MAX 100 μF × × = (EQ. 6) LESR V IN V OUT – ()V OUT f s V IN × V PP MAX ×  × ≥ (EQ. 7) L 2CVO ⋅⋅ ΔI ()2  ΔV MAX ΔIESR ⋅ () – ≤ (EQ. 8) L 1.25 () C ⋅ ΔI ()2  ΔV MAX ΔI ESR ⋅ () – V IN V O – ⎝⎠ ⎛⎞ ≤ (EQ. 9) L V IN V OUT – () V OUT × V IN f s × I OUT MAX 3  ×  ≅ (EQ. 10) I RMS MAX V OUT V IN  I OUT MAX 2 1 12  V IN V OUT – Lf s ×  V OUT V IN  × ⎝⎠ ⎜⎟ ⎛⎞ 2 × + ⎝⎠ ⎜⎟ ⎛⎞ × = (EQ. 11) ISL65426 

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