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FAN6520A Datasheet(PDF) 8 Page - Fairchild Semiconductor |
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FAN6520A Datasheet(HTML) 8 Page - Fairchild Semiconductor |
8 / 15 page ©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6520A Rev. 1.0.5 8 Feedback Compensation Figure 7 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the SW node. The PWM wave is smoothed by the output LC filter (LOUT and COUT). Figure 7. Voltage Mode Buck Converter Compensation Design The modulator transfer function is the small-signal trans- fer function of VOUT/VCOMP. This function is dominated by a DC gain and the output filter (LOUT and COUT), with a double-pole break frequency at FLC and a zero at FESR. The DC gain of the modulator is the input voltage (VIN) divided by the peak-to-peak oscillator voltage ( ΔV OSC. ) The following equations define the modulator break fre- quencies as a function of the output LC filter: The compensation network consists of the error amplifier (internal to the FAN6520A) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed-loop transfer function with the highest 0dB crossing frequency (F0dB) and adequate phase mar- gin. Phase margin is the difference between the closed- loop phase at F0dB and 180 degrees. The equations below relate the compensation network’s poles, zeros, and gain to the components (R1, R2, R3, C1, C2, and C3), shown in Figure 7. Use the following steps to locate the poles and zeros of the compensation network: 1. Pick gain (R2/R1) for the desired converter band- width. 2. Place the first zero below the filter’s double pole (~75% FLC). 3. Place the second zero at filter’s double pole. 4. Place the first pole at the ESR zero. 5. Place the second pole at half the switching fre- quency. 6. Check the gain against the error amplifier’s open- loop gain. 7. Estimate phase margin. Repeat if necessary. Figure 8 shows an asymptotic plot of the DC-DC con- verter’s gain vs. frequency. The actual modulator gain has a high gain peak due to the high Q factor of the out- put filter and is not shown in Figure 8. Using the above guidelines should give a compensation gain similar to the curve plotted. The open-loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The closed-loop gain is constructed on the graph of Fig- ure 8 by adding the modulator gain (in dB) to the com- pensation gain (in dB). This is equivalent to multiplying the modulator transfer function by the compensation transfer function and plotting the gain. The compensation gain uses external impedance net- works ZFB and ZIN to provide a stable high bandwidth overall loop. A stable control loop has a gain crossing with a –20dB/decade slope and a phase margin greater than 45°. Include worst-case component variations when determining phase margin. ZFB COMP FB +VOUT Q2 LOUT COUT +5V VIN SW 0.8V ERROR AMP PWM OSC DETAILED COMPENSATION COMPONENTS COMP FB 0.8V ERROR AMP C1 R2 C3 R3 C2 R1 Z IN V OUT ZFB ZIN F LC 1 2 π LC × ------------------------- = (3) F ESR 1 2 π ESR × C × ------------------------------------ = (4) F Z1 1 2 πR 2C1 ---------------------- = (5) F P1 1 2 πR 2 C 1C2 C 1 C 2 + -------------------- ⎝⎠ ⎛⎞ ----------------------------------------- = (6) F Z2 1 2 πC 3 R1 R 3 + () ---------------------------------------- = (7) F P2 1 2 πR 3C3 ---------------------- = (8) |
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