Electronic Components Datasheet Search |
|
FAN5236 Datasheet(PDF) 10 Page - Fairchild Semiconductor |
|
FAN5236 Datasheet(HTML) 10 Page - Fairchild Semiconductor |
10 / 20 page PRODUCT SPECIFICATION FAN5236 10 REV. 1.1.9 7/12/04 Figure 8. Noise-susceptible In-Phase operation for DDR2 These problems are nicely solved by delaying the 2nd con- verter’s clock by 90° as shown in Figure 9. In this way, all switching transitions in one converter take place far away from the decision points of the other converter. Figure 9. Optimal 90° phasing for DDR2 Initialization and Soft Start Assuming EN is high, FAN5236 is initialized when VCC exceeds the rising UVLO threshold. Should VCC drop below the UVLO threshold, an internal Power-On Reset function disables the chip. The voltage at the positive input of the error amplifier is lim- ited by the voltage at the SS pin which is charged with a 5 µA current source. Once CSS has charged to VREF (0.9V) the output voltage will be in regulation. The time it takes SS to reach 0.9V is: where T0.9 is in seconds if CSS is in µF. When SS reaches 1.5V, the Power Good outputs are enabled and hysteretic mode is allowed. The converter is forced into PWM mode during soft start. Operation Mode Control The mode-control circuit changes the converter’s mode of operation from PWM to Hysteretic and visa versa, based on the voltage polarity of the SW node when the lower MOS- FET is conducting and just before the upper MOSFET turns on. For continuous inductor current, the SW node is negative when the lower MOSFET is conducting and the converters operate in fixed-frequency PWM mode as shown in Figure 10. This mode of operation achieves high efficiency at nomi- nal load. When the load current decreases to the point where the inductor current flows through the lower MOSFET in the ‘reverse’ direction, the SW node becomes positive, and the mode is changed to hysteretic, which achieves higher effi- ciency at low currents by decreasing the effective switching frequency. To prevent accidental mode change or "mode chatter" the transition from PWM to Hysteretic mode occurs when the SW node is positive for eight consecutive clock cycles (see Figure 10). The polarity of the SW node is sampled at the end of the lower MOSFET’s conduction time. At the transi- tion between PWM and hysteretic mode both the upper and lower MOSFETs are turned off. The phase node will ‘ring’ based on the output inductor and the parasitic capacitance on the phase node and settle out at the value of the output volt- age. The boundary value of inductor current, where current becomes discontinuous, can be estimated by the following expression. VDDQ VTT CLK VDDQ VTT CLK T 0.9 0.9 C SS × 5 ----------------------- = (1) I LOAD DIS () V IN V OUT – ()V OUT 2F SWLOUTVIN -------------------------------------------------- = (2) Figure 10. Transitioning between PWM and Hysteretic Mode PWM Mode Hysteretic Mode y Hysteretic Mode y PWM Mode ste e e 12 3 4 56 7 8 V CORE V V I L 0 V CORE V V I L 0 ys de 1 Hyy 2 3 4 5 67 8 |
Similar Part No. - FAN5236 |
|
Similar Description - FAN5236 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |