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AM29SL400C Datasheet(PDF) 4 Page - Advanced Micro Devices

Part No. AM29SL400C
Description  4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory
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Maker  AMD [Advanced Micro Devices]
Homepage  http://www.amd.com
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AM29SL400C Datasheet(HTML) 4 Page - Advanced Micro Devices

 
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Am29SL400C
Am29SL400C_00_A6 January 23, 2007
D A TA
SH EE T
General Description
The Am29SL400C is an 4Mbit, 1.8 V volt-only Flash memory
organized as 524,288 bytes or 262,144 words. The device is
offered in 48-pin TSOP and 48-ball FBGA packages. The
word-wide data (x16) appears on DQ15–DQ0; the byte-wide
(x8) data appears on DQ7–DQ0. This device is designed to
be programmed and erased in-system with a single 1.8 volt
VCC supply. No VPP is required for write or erase operations.
The device can also be programmed in standard EPROM
programmers.
The standard device offers access times of 100, 110, 120,
and 150 ns, allowing high speed microprocessors to operate
without wait states. To eliminate bus contention the device
has separate chip enable (CE#), write enable (WE#) and
output enable (OE#) controls.
The device requires only a single 1.8 volt power supply for
both read and write functions. Internally generated and regu-
lated voltages are provided for the program and erase opera-
tions.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands
are written to the command register using standard micro-
processor write timings. Register contents serve as input to
an internal state-machine that controls the erase and pro-
gramming circuitry. Write cycles also internally latch ad-
dresses and data needed for the programming and erase
operations. Reading data out of the device is similar to read-
ing from other Flash or EPROM devices.
Device programming occurs by executing the program com-
mand sequence. This initiates the Embedded Program al-
gorithm—an internal algorithm that automatically times the
program pulse widths and verifies proper cell margin. The
Unlock Bypass mode facilitates faster programming times
by requiring only two write cycles to program data instead of
four.
Device erasure occurs by executing the erase command se-
quence. This initiates the Embedded Erase algorithm—an
internal algorithm that automatically preprograms the array
(if it is not already programmed) before executing the erase
operation. During erase, the device automatically times the
erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase op-
eration is complete by observing the RY/BY# pin, or by read-
ing the DQ7 (Data# Polling) and DQ6 (toggle) status bits.
After a program or erase cycle has been completed, the de-
vice is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data con-
tents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection measures include a low VCC de-
tector that automatically inhibits write operations during
power transitions. The hardware sector protection feature
disables both program and erase operations in any combina-
tion of the sectors of memory. This can be achieved in-sys-
tem or via programming equipment.
The Erase Suspend feature enables the user to put erase
on hold for any period of time to read data from, or program
data to, any sector that is not selected for erasure. True
background erase can thus be achieved.
The hardware RESET# pin terminates any operation in
progress and resets the internal state machine to reading
array data. The RESET# pin may be tied to the system reset
circuitry. A system reset would thus also reset the device,
enabling the system microprocessor to read the boot-up
firmware from the Flash memory.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of time, the
device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power con-
sumption is greatly reduced in both these modes.
AMD’s Flash technology combines years of Flash memory
manufacturing experience to produce the highest levels of
quality, reliability and cost effectiveness. The device electri-
cally erases all bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is programmed using
hot electron injection.


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