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AM49LV6408M Datasheet(PDF) 5 Page - SPANSION

Part No. AM49LV6408M
Description  Stacked Multi-chip Package (MCP) 64 Mbit (4 M x 16 bit) Flash Memory and 8 Mbit (512K x 16-Bit)
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Maker  SPANSION [SPANSION]
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AM49LV6408M Datasheet(HTML) 5 Page - SPANSION

 
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November 5, 2003
Am49LV6408M
3
ADV ANCE
I N FO RMAT I O N
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 4
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Requirements for Reading Array Data ................................... 11
Page Mode Read ................................................................ 11
Writing Commands/Command Sequences ............................ 11
Write Buffer ......................................................................... 11
Accelerated Program Operation .......................................... 11
Autoselect Functions ........................................................... 11
Automatic Sleep Mode ........................................................... 12
RESET#: Hardware Reset Pin ............................................... 12
Output Disable Mode .............................................................. 12
Table 2. Am29LV640MT Top Boot Sector Architecture ..................12
Table 3. Am29LV640MB Bottom Boot Sector Architecture .............15
Sector Group Protection and Unprotection ............................. 18
Table 4. Am29LV640MT Top Boot Sector Protection .....................18
Table 5. Am29LV640MB Bottom Boot Sector Protection ................18
Write Protect (WP#) ................................................................ 19
Temporary Sector Group Unprotect ....................................... 19
Figure 1. Temporary Sector Group Unprotect Operation................ 19
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 20
SecSi (Secured Silicon) Sector Flash Memory Region .......... 21
Table 6. SecSi Sector Contents ......................................................21
Figure 3. SecSi Sector Protect Verify.............................................. 22
Hardware Data Protection ...................................................... 22
Low VCC Write Inhibit ......................................................... 22
Write Pulse “Glitch” Protection ............................................ 22
Logical Inhibit ...................................................................... 22
Power-Up Write Inhibit ......................................................... 22
Common Flash Memory Interface (CFI) . . . . . . . 22
Command Definitions . . . . . . . . . . . . . . . . . . . . . 25
Reading Array Data ................................................................ 25
Reset Command ..................................................................... 26
Autoselect Command Sequence ............................................ 26
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 26
Word Program Command Sequence ..................................... 26
Unlock Bypass Command Sequence .................................. 27
Write Buffer Programming ................................................... 27
Accelerated Program ........................................................... 28
Figure 4. Write Buffer Programming Operation............................... 29
Figure 5. Program Operation .......................................................... 30
Program Suspend/Program Resume Command Sequence ... 30
Figure 6. Program Suspend/Program Resume............................... 31
Chip Erase Command Sequence ........................................... 31
Sector Erase Command Sequence ........................................ 31
Figure 7. Erase Operation............................................................... 32
Erase Suspend/Erase Resume Commands ........................... 32
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 34
DQ7: Data# Polling ................................................................. 34
Figure 8. Data# Polling Algorithm ................................................... 34
DQ6: Toggle Bit I .................................................................... 35
Figure 9. Toggle Bit Algorithm........................................................ 36
DQ2: Toggle Bit II ................................................................... 36
Reading Toggle Bits DQ6/DQ2 ............................................... 36
DQ5: Exceeded Timing Limits ................................................ 37
DQ3: Sector Erase Timer ....................................................... 37
DQ1: Write-to-Buffer Abort ..................................................... 37
Table 12. Write Operation Status ................................................... 37
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 38
Figure 10. Maximum Negative Overshoot Waveform ................... 38
Figure 11. Maximum Positive Overshoot Waveform..................... 38
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 38
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
Pseudo SRAM DC and
Operating Characteristics . . . . . . . . . . . . . . . . . . 40
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 12. Test Setup.................................................................... 41
Table 13. Test Specifications ......................................................... 41
Key to Switching Waveforms. . . . . . . . . . . . . . . . 41
Figure 13. Input Waveforms and Measurement Levels ................. 41
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42
Flash Read-Only Operations ................................................. 42
Figure 14. Read Operation Timings ............................................... 42
Figure 15. Page Read Timings ...................................................... 43
Hardware Reset (RESET#) .................................................... 44
Figure 16. Reset Timings ............................................................... 44
Erase and Program Operations .............................................. 45
Figure 17. Program Operation Timings.......................................... 46
Figure 18. Accelerated Program Timing Diagram .......................... 46
Figure 19. Chip/Sector Erase Operation Timings .......................... 47
Figure 20. Data# Polling Timings
(During Embedded Algorithms)...................................................... 48
Figure 21. Toggle Bit Timings (During Embedded Algorithms)...... 49
Figure 22. DQ2 vs. DQ6................................................................. 49
Temporary Sector Unprotect .................................................. 50
Figure 23. Temporary Sector Group Unprotect Timing Diagram ... 50
Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 51
Alternate CE# Controlled Erase and Program Operations ..... 52
Figure 25. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.......................................................................... 53
Pseudo SRAM AC Characteristics . . . . . . . . . . . 54
Power Up Time ....................................................................... 54
Read Cycle ............................................................................. 54
Figure 26. Pseudo SRAM Read Cycle—Address Controlled......... 54
Figure 27. Pseudo SRAM Read Cycle........................................... 55
Write Cycle ............................................................................. 56
Figure 28. Pseudo SRAM Write Cycle—WE# Control ................... 56
Figure 29. Pseudo SRAM Write Cycle—CE1#s Control ................ 57
Flash Erase And Programming Performance . . 58
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 58
BGA Package Capacitance . . . . . . . . . . . . . . . . . 58
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 60
TLB069—69-Ball Fine-pitch Ball Grid Array (FBGA)
8 x 10 mm Package ................................................................ 60
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 61


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