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AM75PDL191CHHA Datasheet(PDF) 11 Page - SPANSION |
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AM75PDL191CHHA Datasheet(HTML) 11 Page - SPANSION |
11 / 129 page January 14, 2004 Am75PDL191CHHa/Am75PDL193CHHa 9 ADV ANCE I N FO RMAT I O N DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 63 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 10. Test Setup..................................................................... 64 Figure 11. Input Waveforms and Measurement Levels .................. 64 pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 65 CE#1ps Timing ....................................................................... 65 Figure 12. Timing Diagram for Alternating Between Pseudo SRAM and Flash................................................. 65 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 66 Read-Only Operations – Am29PDL127H ............................... 66 Read-Only Operations – Am29PDL129H ............................... 66 Figure 13. Read Operation Timings ................................................ 67 Figure 14. Page Read Operation Timings....................................... 67 Hardware Reset (RESET#) .................................................... 68 Figure 15. Reset Timings ................................................................ 68 Erase and Program Operations .............................................. 69 Figure 16. Program Operation Timings........................................... 70 Figure 17. Accelerated Program Timing Diagram........................... 70 Figure 18. Chip/Sector Erase Operation Timings ........................... 71 Figure 19. Back-to-back Read/Write Cycle Timings ....................... 72 Figure 20. Data# Polling Timings (During Embedded Algorithms).. 72 Figure 21. Toggle Bit Timings (During Embedded Algorithms)....... 73 Figure 22. DQ2 vs. DQ6.................................................................. 73 Temporary Sector Unprotect .................................................. 74 Figure 23. Temporary Sector Unprotect Timing Diagram ............... 74 Figure 24. Sector/Sector Block Protect and Unprotect Timing Diagram .............................................................. 75 Alternate CE# Controlled Erase and Program Operations ..... 76 Figure 25. Flash Alternate CE# Controlled Write (Erase/Program) Operation Timings........................................................................... 77 Erase And Programming Performance . . . . . . . . 78 Latchup Characteristics . . . . . . . . . . . . . . . . . . . 78 Package Pin Capacitance . . . . . . . . . . . . . . . . . . 78 Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 78 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 79 Table 1. Am29DL640H Device Bus Operations ..............................79 Word/Byte Configuration ........................................................ 79 Requirements for Reading Array Data ................................... 79 Writing Commands/Command Sequences ............................ 80 Accelerated Program Operation .......................................... 80 Autoselect Functions ........................................................... 80 Simultaneous Read/Write Operations with Zero Latency ....... 80 Standby Mode ........................................................................ 80 Automatic Sleep Mode ........................................................... 80 RESET#: Hardware Reset Pin ............................................... 81 Output Disable Mode .............................................................. 81 Table 2. Am29DL640H Sector Architecture ....................................81 Table 3. Bank Address ....................................................................84 SecSi TM Sector Addresses.............................................................. 84 Autoselect Mode ..................................................................... 84 Sector/Sector Block Protection and Unprotection .................. 85 Table 5. Am29DL640H Boot Sector/Sector Block Addresses for Pro- tection/Unprotection ........................................................................85 Write Protect (WP#) ................................................................ 85 Table 6. WP#/ACC Modes ..............................................................86 Temporary Sector Unprotect .................................................. 86 Figure 1. Temporary Sector Unprotect Operation........................... 86 Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 87 SecSi™ (Secured Silicon) Sector Flash Memory Region ............................................................ 88 Figure 3. SecSi Sector Protect Verify............................................. 89 Hardware Data Protection ...................................................... 89 Low VCC Write Inhibit ......................................................... 89 Write Pulse “Glitch” Protection ............................................ 89 Logical Inhibit ....................................................................... 89 Power-Up Write Inhibit ......................................................... 89 Common Flash Memory Interface (CFI) . . . . . . . 89 Table 7. CFI Query Identification String .......................................... 90 System Interface String................................................................... 90 Table 9. Device Geometry Definition .............................................. 91 Table 10. Primary Vendor-Specific Extended Query ...................... 92 Command Definitions . . . . . . . . . . . . . . . . . . . . . 93 Reading Array Data ................................................................ 93 Reset Command ..................................................................... 93 Autoselect Command Sequence ............................................ 93 Enter SecSi™ Sector/Exit SecSi Sector Command Sequence .............................................................. 93 Word Program Command Sequence ...................................... 94 Unlock Bypass Command Sequence .................................. 94 Figure 4. Program Operation ......................................................... 95 Chip Erase Command Sequence ........................................... 95 Sector Erase Command Sequence ........................................ 95 Figure 5. Erase Operation.............................................................. 96 Erase Suspend/Erase Resume Commands ........................... 96 Table 11. Am29DL640H Command Definitions .............................. 97 Write Operation Status . . . . . . . . . . . . . . . . . . . . 98 DQ7: Data# Polling ................................................................. 98 Figure 6. Data# Polling Algorithm .................................................. 98 RY/BY#: Ready/Busy# ............................................................ 99 DQ6: Toggle Bit I .................................................................... 99 Figure 7. Toggle Bit Algorithm........................................................ 99 DQ2: Toggle Bit II ................................................................. 100 Reading Toggle Bits DQ6/DQ2 ............................................. 100 DQ5: Exceeded Timing Limits .............................................. 100 DQ3: Sector Erase Timer ..................................................... 100 Table 12. Write Operation Status ................................................. 101 Absolute Maximum Ratings . . . . . . . . . . . . . . . 102 Figure 8. Maximum Negative Overshoot Waveform .................... 102 Figure 9. Maximum Positive Overshoot Waveform...................... 102 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 10. I CC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ........................................................... 104 Figure 11. Typical I CC1 vs. Frequency .......................................... 104 pSRAM DC Characteristics . . . . . . . . . . . . . . . . 105 Recommended DC Operating Conditions (Note 1) .............. 105 Capacitance (f= 1MHz, TA = 25×C) ..................................... 105 DC and Operating Characteristics ........................................ 105 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 12. Test Setup.................................................................. 106 Figure 13. Input Waveforms and Measurement Levels ............... 106 PSRAM AC Characteristics . . . . . . . . . . . . . . . . 107 CE#s Timing ......................................................................... 107 Figure 14. Timing Diagram for Alternating Between Pseudo SRAM to Flash................................................. 107 Figure 15. Timing Waveform of Power-up ................................... 107 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 108 Read-Only Operations ......................................................... 108 Figure 16. Read Operation Timings ............................................. 108 Hardware Reset (RESET#) .................................................. 109 Figure 17. Reset Timings ............................................................. 109 |
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