COM20020I3V-HD datasheet(3/65 Pages) SMSC

Part #	COM20020I3V-HD

Description	5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Download	65 Pages

Scroll/Zoom	100%

Manufacturer	SMSC [SMSC Corporation]

Direct Link	http://www.smsc.com

Logo

3 / 65 page

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

SMSC COM20020I 3.3V

Page 3

Revision 12-06-06

DATASHEET

TABLE OF CONTENTS

2.0

GENERAL DESCRIPTION..............................................................................................................................5

3.0

PIN CONFIGURATIONS .................................................................................................................................6

4.0

DESCRIPTION OF PIN FUNCTIONS FOR TQFP ..........................................................................................8

5.0

PROTOCOL DESCRIPTION .........................................................................................................................11

5.1

NETWORK PROTOCOL ..................................................................................................................................11

5.2

DATA RATES ...............................................................................................................................................11

5.3

NETWORK RECONFIGURATION.......................................................................................................................12

5.4

BROADCAST MESSAGES ...............................................................................................................................12

5.5

EXTENDED TIMEOUT FUNCTION .....................................................................................................................12

5.6

LINE PROTOCOL ..........................................................................................................................................13

6.0

SYSTEM DESCRIPTION...............................................................................................................................15

6.1

MICROCONTROLLER INTERFACE ....................................................................................................................15

6.2

TRANSMISSION MEDIA INTERFACE .................................................................................................................19

7.0

FUNCTIONAL DESCRIPTION ......................................................................................................................24

7.1

MICROSEQUENCER ......................................................................................................................................24

7.2

INTERNAL REGISTERS...........................................................................................................................25

7.3

INTERNAL RAM ............................................................................................................................................35

7.4

COMMAND CHAINING....................................................................................................................................40

7.5

INITIALIZATION SEQUENCE ............................................................................................................................42

7.6

IMPROVED DIAGNOSTICS ..............................................................................................................................42

8.0

OPERATIONAL DESCRIPTION ...................................................................................................................45

8.1

MAXIMUM GUARANTEED RATINGS* ................................................................................................................45

8.2

DC ELECTRICAL CHARACTERISTICS ...............................................................................................................45

9.0

TIMING DIAGRAMS......................................................................................................................................48

10.0

PACKAGE OUTLINES..................................................................................................................................60

11.0

APPENDIX A.................................................................................................................................................62

12.0

APPENDIX B.................................................................................................................................................65

12.1

SOFTWARE IDENTIFICATION OF THE COM20020I REV B, REV C AND REV D .....................................................65

LIST OF FIGURES

Figure 1 - COM20020I OPERATION ...........................................................................................................................10

Figure 2 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE ...............................................16

Figure 3 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE ......................................17

Figure 4 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE...............................................................................18

Figure 5 - COM20020I NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS ................................................20

Figure 6 - DIPULSE WAVEFORM FOR DATA OF 1-1-0 .............................................................................................20

Figure 7 - INTERNAL BLOCK DIAGRAM ....................................................................................................................22

Figure 8 – SEQUENTIAL ACCESS OPERATION........................................................................................................35

Figure 9 – RAM BUFFER PACKET CONFIGURATION ..............................................................................................38

Figure 10 - COMMAND CHAINING STATUS REGISTER QUEUE ...............................................................................40

Figure 11 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE ..................................................48

Figure 12 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE ..................................................49

Figure 13 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE.................................................50

Similar Part No. - COM20020I3V-HD

Manufacturer	Part #	Datasheet	Description
SMSC Corporation	COM20020I3V-HD	478Kb / 69P	5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

More results

Similar Description - COM20020I3V-HD

Manufacturer	Part #	Datasheet	Description
Microchip Technology	COM20020ILJP	412Kb / 72P	5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM Revision 12-05-06
SMSC Corporation	COM20020I	415Kb / 72P	5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
	COM20020I_0609	478Kb / 69P	5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
	COM20019I	391Kb / 65P	Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
	COM20019I_0610	490Kb / 70P	Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
	COM20019I	505Kb / 65P	Low Cost ARCNET(ANSI 878.1) Controller with 2k X 8 On-Board RAM
	COM20019	454Kb / 81P	Low Cost ARCNET (ANSI 878.1) Controller with 2K x 8 On-Board RAM
	COM20019I	392Kb / 65P	Low Cost ARCNET (ANSI 878.1) Controller with 2K x 8 On-Board RAM
	COM20022I-3.3V	474Kb / 73P	10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
	COM200221	514Kb / 82P	10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

More results

COM20020I3V-HD Datasheet(PDF) 3 Page - SMSC Corporation

COM20020I3V-HD Datasheet(HTML) 3 Page - SMSC Corporation

Similar Part No. - COM20020I3V-HD

Similar Description - COM20020I3V-HD

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

Datasheet Download

Link URL