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COM20020I3V-HD Datasheet(PDF) 3 Page - SMSC Corporation |
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COM20020I3V-HD Datasheet(HTML) 3 Page - SMSC Corporation |
3 / 65 page 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM SMSC COM20020I 3.3V Page 3 Revision 12-06-06 DATASHEET TABLE OF CONTENTS 2.0 GENERAL DESCRIPTION..............................................................................................................................5 3.0 PIN CONFIGURATIONS .................................................................................................................................6 4.0 DESCRIPTION OF PIN FUNCTIONS FOR TQFP ..........................................................................................8 5.0 PROTOCOL DESCRIPTION .........................................................................................................................11 5.1 NETWORK PROTOCOL ..................................................................................................................................11 5.2 DATA RATES ...............................................................................................................................................11 5.3 NETWORK RECONFIGURATION.......................................................................................................................12 5.4 BROADCAST MESSAGES ...............................................................................................................................12 5.5 EXTENDED TIMEOUT FUNCTION .....................................................................................................................12 5.6 LINE PROTOCOL ..........................................................................................................................................13 6.0 SYSTEM DESCRIPTION...............................................................................................................................15 6.1 MICROCONTROLLER INTERFACE ....................................................................................................................15 6.2 TRANSMISSION MEDIA INTERFACE .................................................................................................................19 7.0 FUNCTIONAL DESCRIPTION ......................................................................................................................24 7.1 MICROSEQUENCER ......................................................................................................................................24 7.2 INTERNAL REGISTERS...........................................................................................................................25 7.3 INTERNAL RAM ............................................................................................................................................35 7.4 COMMAND CHAINING....................................................................................................................................40 7.5 INITIALIZATION SEQUENCE ............................................................................................................................42 7.6 IMPROVED DIAGNOSTICS ..............................................................................................................................42 8.0 OPERATIONAL DESCRIPTION ...................................................................................................................45 8.1 MAXIMUM GUARANTEED RATINGS* ................................................................................................................45 8.2 DC ELECTRICAL CHARACTERISTICS ...............................................................................................................45 9.0 TIMING DIAGRAMS......................................................................................................................................48 10.0 PACKAGE OUTLINES..................................................................................................................................60 11.0 APPENDIX A.................................................................................................................................................62 12.0 APPENDIX B.................................................................................................................................................65 12.1 SOFTWARE IDENTIFICATION OF THE COM20020I REV B, REV C AND REV D .....................................................65 LIST OF FIGURES Figure 1 - COM20020I OPERATION ...........................................................................................................................10 Figure 2 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE ...............................................16 Figure 3 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE ......................................17 Figure 4 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE...............................................................................18 Figure 5 - COM20020I NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS ................................................20 Figure 6 - DIPULSE WAVEFORM FOR DATA OF 1-1-0 .............................................................................................20 Figure 7 - INTERNAL BLOCK DIAGRAM ....................................................................................................................22 Figure 8 – SEQUENTIAL ACCESS OPERATION........................................................................................................35 Figure 9 – RAM BUFFER PACKET CONFIGURATION ..............................................................................................38 Figure 10 - COMMAND CHAINING STATUS REGISTER QUEUE ...............................................................................40 Figure 11 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE ..................................................48 Figure 12 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE ..................................................49 Figure 13 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE.................................................50 |
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