LAN8187 datasheet(49/72 Pages) SMSC

Part #	LAN8187

Description	짹15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWRTM

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±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWRTM

Datasheet

SMSC LAN8187/LAN8187I

49

Revision 1.0 (12-14-06)

DATASHEET

5.3

Interrupt Management

The Management interface supports an interrupt capability that is not a part of the IEEE 802.3

specification. It generates an active low asynchronous interrupt signal on the nINT output whenever

certain events are detected as setup by the Interrupt Mask Register 30.

The Interrupt system on the SMSC LAN8187/8187I has two modes, a Primary Interrupt mode and an

Alternative Interrupt mode. Both systems will assert the nINT pin low when the corresponding mask

bit is set, the difference is how they de-assert the output interrupt signal nINT.

The Primary interrupt mode is the default interrupt mode after a power-up or hard reset, the Alternative

interrupt mode would need to be setup again after a power-up or hard reset.

5.3.1

Primary Interrupt System

The Primary Interrupt system is the default interrupt mode, (Bit 17.6 = ‘0’). The Primary Interrupt

System is always selected after power-up or hard reset.

To set an interrupt, set the corresponding mask bit in the interrupt Mask register 30 (see Table 5.45).

Then when the event to assert nINT is true, the nINT output will be asserted.

When the corresponding Event to De-Assert nINT is true, then the nINT will be de-asserted.

Note: The ENERGYON bit 17.1 is defaulted to a ‘1’ at the start of the signal acquisition process,

therefore the Interrupt source flag 29.7 will also read as a ‘1’ at power-up. If no signal is

present, then both 17.1 and 29.7 wil clear within a few milliseconds.

5.3.2

Alternate Interrupt System

The Alternative method is enabled by writing a ‘1’ to 17.6 (ALTINT).

Table 5.45 Interrupt Management Table.

Mask

Interrupt Source Flag

Interrupt Source

Event to Assert nINT

Event to De-Assert nINT

30.7

29.7

ENERGYON

17.1

ENERGYON

Rising 17.1a

a.

If the mask bit is enabled and nINT has been de-asserted while ENERGYON is still high, nINT will assert for

256 ms, approximately one second after ENERGYON goes low when the Cable is unplugged. To prevent an

unexpected assertion of nINT, the ENERGYON interrupt mask should always be cleared as part of the

ENERGYON interrupt service routine.

Falling 17.1 or

Reading register 29

30.6

29.6

Auto-Negotiation

complete

1.5

Auto-Negotiate

Complete

Rising 1.5

Falling 1.5 or

Reading register 29

30.5

29.5

Remote Fault Detected

1.4

Remote Fault

Rising 1.4

Falling 1.4, or

Reading register 1 or

Reading register 29

30.4

29.4

Link Down

1.2

Link Status

Falling 1.2

Reading register 1 or

Reading register 29

30.3

29.3

Auto-Negotiation LP

Achnowledge

5.14

Acknowledge

Rising 5.14

Falling 5.14 or

Read register 29

30.2

29.2

Parallel Detection Fault

6.4

Parallel Detection

Fault

Rising 6.4

Falling 6.4 or

Reading register 6, or

Reading register 29 or

Re-AutoNegotaite or

Link down

30.1

29.1

Auto-Negotiation Page

Received

6.1

Page Received

Rising 6.1

Falling of 6.1 or

Reading register 6, or

Reading register 29

Re-AutoNegotatie, or

Link Down.

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