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EMC2300 Datasheet(PDF) 76 Page - SMSC Corporation

Part No. EMC2300
Description  Fan Control Device with High Frequency PWM and Temperature Monitors
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Maker  SMSC [SMSC Corporation]
Homepage  http://www.smsc.com
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EMC2300 Datasheet(HTML) 76 Page - SMSC Corporation

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Fan Control Device with High Frequency PWM and Temperature Monitors
Datasheet
Revision 0.2 (06-14-06)
76
SMSC EMC2300
DATASHEET
9.2
SMBus Interface
Figure 9.4 SMBus Timing
Note 9.5
The SMBus timing (e.g., max clock frequency of 400kHz) specified exceeds that specified
in the System Management Bus Specification, Rev 1.1. This corresponds to the maximum
clock frequency for fast mode devices on the I2C bus. See “The I2C Bus Specification,”
version 2.0, Dec. 1998.
Note 9.6
At 400kHz, spikes of a maximum pulse width of 50ns must be suppressed by the input
filter.
Note 9.7
If using 100 kHz clock frequency, the next data bit output to the SDA line will be 1250 ns
(1000 ns (TR max) + 250 ns (TSU:DAT min) @ 100 kHz) before the SCLK line is released.
Table 9.2 SMBus Timing
SYMBOL
PARAMETER
LIMITS
UNITS
COMMENTS
MIN
MAX
Fsmb
SMB Operating Frequency
10
400
kHz
Note 9.5
Tsp
Spike Suppression
50
ns
Note 9.6
Tbuf
Bus free time between Stop and Start
Condition
1.3
μs
Thd:sta
Hold time after (Repeated) Start Condition.
After this period, the first clock is
generated.
0.6
μs
Tsu:sta
Repeated Start Condition setup time
0.6
μs
Tsu:sto
Stop Condition setup time
0.6
μs
Thd:dat
Data hold time
0.3
0.9
μs
Tsu:dat
Data setup time
100
ns
Note 9.7
Tlow
Clock low period
1.3
μs
Thigh
Clock high period
0.6
μs
Tf
Clock/Data Fall Time
20+0.1Cb
300
ns
Tr
Clock/Data Rise Time
20+0.1Cb
300
ns
Cb
Capacitive load for each bus line
400
pF
P
t
BUF
t
R
t
HD;STA
P
S
S
t
HD;STA
t
LOW
t
HD;DAT
t
HIGH
t
F
t
SU;DAT
t
SU;STA
t
SU;STO
SCLK
SDA


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