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EMC2300 Datasheet(PDF) 73 Page - SMSC Corporation

Part No. EMC2300
Description  Fan Control Device with High Frequency PWM and Temperature Monitors
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Maker  SMSC [SMSC Corporation]
Homepage  http://www.smsc.com
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EMC2300 Datasheet(HTML) 73 Page - SMSC Corporation

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Fan Control Device with High Frequency PWM and Temperature Monitors
Datasheet
SMSC EMC2300
73
Revision 0.2 (06-14-06)
DATASHEET
8.2.28
Registers 94h-96h: PWMx Option Registers
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
Table 8.52 TACH Option Register Bits
BIT
NAME
R/W DEFAULT
DESCRIPTION
0
SLOW
R/W
0
‘0’ - Force TACH reading register to FFFEh if number of tach edges
detected is greater than 0 but less than the programmed number of
edges
‘1’ - Force TACH reading register to FFFFh if number of tach edges
detected is greater than 0 but less than the programmed number of
edges
1
EDG0
R/W
0
Determines the number of edges necessary for a valid TACH reading.
00 = 2 edges
01 = 3 edges
10 = 5 edges
11 = 9 edges
2
EDG1
R/W
1
3
MODE
R/W
0
Determines TACH reading mode
‘0’ Mode 1 - standard operating mode
‘1’ Mode 2 - only check measure TACH while PWM output is high.
4
3EDG
R/W
0
This bit is used when the TACH Mode is configured for Mode 2 only.
‘0’ - don’t ignore 1st 3 TACH edges after PWM transitions from low to
high
‘1’ - ignore first 3 edges after guard time
Note:
This bit has been added to support a small sampling of fans that
emit irregular tach pulses when the PWM transitions ‘ON’.
Typically, the guard time is sufficient for most fans.
5
RES
R/W
0
Reserved
6
RES
R/W
0
Reserved
7
RES
R/W
0
Reserved
Table 8.53 Registers 94h-96h: PWMx Option Registers
Register
Address
Read/
Write
Register
Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
94h
R/W
PWM1 Option
RES
RES
OPP
GRD1
GRD0
SZEN
UPDT1
UPDT0
0Ch
95h
R/W
PWM2 Option
RES
RES
OPP
GRD1
GRD0
SZEN
UPDT1
UPDT0
0Ch
96h
R/W
PWM3 Option
RES
RES
OPP
GRD1
GRD0
SZEN
UPDT1
UPDT0
0Ch


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