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EMC2300 Datasheet(PDF) 69 Page - SMSC Corporation

Part No. EMC2300
Description  Fan Control Device with High Frequency PWM and Temperature Monitors
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Maker  SMSC [SMSC Corporation]
Homepage  http://www.smsc.com
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EMC2300 Datasheet(HTML) 69 Page - SMSC Corporation

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Fan Control Device with High Frequency PWM and Temperature Monitors
Datasheet
SMSC EMC2300
69
Revision 0.2 (06-14-06)
DATASHEET
This register contains the following bits:
8.2.23
Register 80h: Interrupt Enable 2 Register
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
This register is used to enable individual fan tach error events to set the corresponding status bits in
the interrupt status registers. This register also contains the group fan tach enable bit (Bit[0] TACH),
which is used to enable fan tach events to force the interrupt pin (INT#) low if interrupts are enabled
(see Bit[2] INTEN of the Special Function register at offset 7Ch).
See Figure 6.3 Interrupt Control on page 24.
This register contains the following bits:
Table 8.43 Configuration Register Bits
BIT
NAME
R/W DEFAULT
DESCRIPTION
0
T3INT
R/W
0
Determines functionality of the TACH3/INT# pin.
‘0’ - TACH3 input
‘1’- INT# output
1
P2INT
R/W
0
Determines the functionality of the PWM2/INT# pin.
‘0’ - PWM2 output.
‘1’ - INT# output.
2
Reserved
R/W
0
Reserved
3
TRDY
R
0
Temperature Reading Ready - indicates that the temperature reading
registers hold valid values.
4
SUREN
R/W
1
Spin-up reduction enable - when set, this bit enables the reduction of the
spin-up time based on feedback from all fan tachometers associated with
each PWM.
5
SMSC
R/W
0
SMSC - Writing to this bit to a value different from the default value may
cause unwanted results.
6
SMSC
R/W
0
SMSC - Writing this bit to a value different than the default value may
cause unwanted results.
7
INIT
R/W
0
Setting the INIT bit to ‘1’ performs a soft reset. This bit is self-clearing.
Soft Reset sets all the registers except the Reading Registers to their
default values.
Table 8.44 Register 80h: Interrupt Enable 2 Register
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
80h
R/W
Interrupt Enable 2 (Fan
Tachs)
RES
RES
RES
TACH4
TACH3
TACH2
TACH1
TACH
1Eh


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