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EMC2300 Datasheet(PDF) 59 Page - SMSC Corporation

Part No. EMC2300
Description  Fan Control Device with High Frequency PWM and Temperature Monitors
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Maker  SMSC [SMSC Corporation]
Homepage  http://www.smsc.com
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EMC2300 Datasheet(HTML) 59 Page - SMSC Corporation

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Fan Control Device with High Frequency PWM and Temperature Monitors
Datasheet
SMSC EMC2300
59
Revision 0.2 (06-14-06)
DATASHEET
8.2.12
Registers 54-5Bh: Fan Tachometer Low Limit
Setting the Lock bit has no effect on these registers.
The Fan Tachometer Low Limit registers indicate the tachometer reading that, if exceeded, the
corresponding bit will be set in the Interrupt Status Register 2 register. This register represents a
number of clock counts between the programmed number of tach edges and therefore as the number
increases, the effective RPM that it represents will decrease. The limit represents a fixed fan speed
(though the TACH measurement options may limit fan speeds that can be measured). See
Section 8.2.3 for a description of the TACH data formatting.
In Auto Fan Control mode, the fan can run at high speeds (100% duty cycle), so care should be taken
in software to ensure that the limit is low enough not to cause sporadic alerts. Note that an interrupt
status event will be generated when the tachometer reading is greater than the minimum tachometer
limit.
The fan tachometer will not cause a bit to be set in the interrupt status register if the current value in
the associated Current PWM Duty registers is 00h or if the PWM is disabled via the PWM
Configuration Register.
Interrupts will never be generated for a fan if its tachometer minimum is set to FFFFh.
8.2.13
Registers 5C-5Eh: PWM Configuration
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
Bits [7:5] Zone/Mode
Bits [7:5] of the PWM Configuration registers associate each PWM with a temperature sensor.
Table 8.21 Registers 54-5Bh: Fan Tachometer Low Limit
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
54h
R/W
Tach1 Minimum LSB
7
6
5
4
3
2
1
0
FFh
55h
R/W
Tach1 Minimum MSB
15
14
13
12
11
10
9
8
FFh
56h
R/W
Tach2 Minimum LSB
7
6
5
4
3
2
1
0
FFh
57h
R/W
Tach2 Minimum MSB
15
14
13
12
11
10
9
8
FFh
58h
R/W
Tach3 Minimum LSB
7
6
5
4
3
2
1
0
FFh
59h
R/W
Tach3 Minimum MSB
15
14
13
12
11
10
9
8
FFh
5Ah
R/W
Tach4 Minimum LSB
7
6
5
4
3
2
1
0
FFh
5Bh
R/W
Tach4 Minimum MSB
15
14
13
12
11
10
9
8
FFh
Table 8.22 Registers 5C-5Eh: PWM Configuration
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
5Ch
R/W
PWM 1 Configuration
ZON2
ZON1
ZON0
INV
RES
SPIN2
SPIN1
SPIN0
62h
5Dh
R/W
PWM 2 Configuration
ZON2
ZON1
ZON0
INV
RES
SPIN2
SPIN1
SPIN0
62h
5Eh
R/W
PWM 3 Configuration
ZON2
ZON1
ZON0
INV
RES
SPIN2
SPIN1
SPIN0
62h


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