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EMC2300 Datasheet(PDF) 48 Page - SMSC Corporation

Part No. EMC2300
Description  Fan Control Device with High Frequency PWM and Temperature Monitors
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Maker  SMSC [SMSC Corporation]
Homepage  http://www.smsc.com
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EMC2300 Datasheet(HTML) 48 Page - SMSC Corporation

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Note: SMSC Test Registers may be read/write registers. Writing these registers can cause unwanted results.
Note 8.1
The PWMx Current Duty Cycle Registers are only writable when the associated fan is in manual mode. In this case, the register is writable
when the start bit is set, but not when the lock bit is set.
Note 8.2
The Lock bit in the Ready/Lock/Start register is locked by the Lock Bit. The START and OVRID bits are always writable, both when the start
bit is set and when the lock bit is set.
Note 8.3
The Interrupt status registers are cleared on a read if no events are active
Note 8.4
The INTEN bit in register 7Ch is always writable, both when the start bit is set and when the lock bit is set.
Note 8.5
In Shutdown Mode (LPMD=1 & START=0) all the H/W Monitoring registers/bits are not accessible except for the following: Bits[2:0] in the
Special Function Register (SFTR) at offset 7Ch and Bits[7:0] in the Configuration register at offset 7Fh.
Note 8.6
These Reserved bits are read/write bits. Writing these bits to a ‘1’ has no effect on the hardware.
Note 8.7
SMSC bits may be read/write bits. Writing these bits to a value other than the default value may cause unwanted results
88h
R
A/D Converter LSbs Reg 4
VCC.3
VCC.2
VCC.1
VCC.0
VCP.3
VCP.2
VCP.1
VCP.0
N/A
No
No
90h
R/W
Tach1 Option
RES
RES
RES
3EDG
MODE
EDG1
EDG0
SLOW
04h
No
No
91h
R/W
Tach2 Option
RES
RES
RES
3EDG
MODE
EDG1
EDG0
SLOW
04h
No
No
92h
R/W
Tach3 Option
RES
RES
RES
3EDG
MODE
EDG1
EDG0
SLOW
04h
No
No
93h
R/W
Tach4 Option
RES
RE S
RES
3EDG
MODE
EDG1
EDG0
SLOW
04h
No
No
94h
R/W
PWM1 Option
RES
Note 8.6
RES
Note 8.6
OPP
GRD1
GRD0
SZEN
UPDT1
UPDT0
0Ch
Yes
No
95h
R/W
PWM2 Option
RES
Note 8.6
RES
Note 8.6
OPP
GRD1
GRD0
SZEN
UPDT1
UPDT0
0Ch
Yes
No
96h
R/W
PWM3 Option
RES
Note 8.6
RES
Note 8.6
OPP
GRD1
GRD0
SZEN
UPDT1
UPDT0
0Ch
Yes
No
FFh
R
SMSC Test Register
TST7
TST 6
TST 5
TST 4
TST3
TST2
TST1
TST0
N/A
No
No
Table 8.1 Register Summary (continued)
Reg
Addr
Read
/Write
Reg Name
Bit 7
MSb
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LSb
Default
Value
Lock
Start


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