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EMC2300 Datasheet(PDF) 26 Page - SMSC Corporation

Part No. EMC2300
Description  Fan Control Device with High Frequency PWM and Temperature Monitors
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Maker  SMSC [SMSC Corporation]
Homepage  http://www.smsc.com
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EMC2300 Datasheet(HTML) 26 Page - SMSC Corporation

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Fan Control Device with High Frequency PWM and Temperature Monitors
Datasheet
Revision 0.2 (06-14-06)
26
SMSC EMC2300
DATASHEET
The INT# pin can be enabled to indicate fan errors. Bit[0] of the Interrupt Enable 2(Fan Tachs) register
(80h) is used to enable this option. This pin will remain low while the associated fan error bit in the
Interrupt Status Register 2 is set.
The INT# pin will remain low while any bit is set in any of the Interrupt Status Registers. Reading the
interrupt status registers will cause the logic to attempt to clear the status bits; however, the status bits
will not clear if the interrupt stimulus is still active. The interrupt enable bit (Special Function Register
bit[2]) should be cleared by software before reading the interrupt status registers to insure that the INT#
pin will be re-asserted while an interrupt event is active, when the INT_EN bit is written to ‘1’ again.
The INT# pin can also be deasserted by issuing an Alert Response Address Call. See the description
in the section titled SMBus Alert Response Address on page 18.
The INT# pin may only become active while the monitor block is operational.
6.6
Low Power Modes
The Hardware Monitor Block can be placed in a low-power mode by writing a ‘0’ to Bit[0] of the
Ready/Lock/Start Register (0x40). The low power mode that is entered is either sleep mode or
shutdown mode as selected using Bit[0] of the Special Function Register (7Ch). These modes do not
reset any of the registers of the Hardware Monitor Block. In both of these modes, the PWM pins are
at 100% duty cycle.
Notes:
START and LPMD bits cannot be modified when the LOCK bit is set.
START bit is located in the Ready/Lock/Start register (40h). LPMD bit is located in the Special
Function Register (7Ch)
6.6.1
Sleep Mode
This is a low power mode in which bias currents are on and the internal oscillator is on, but the A/D
converter and monitoring cycle are turned off. Serial bus communication is still possible with any
register in the Hardware Monitor Block while in this low-power mode.
6.6.2
Shutdown Mode
This is a low power mode in which bias currents are off, the internal oscillator is off, and the the A/D
converter and monitoring cycle are turned off. Serial communication is only possible with Bits[2:0] of
the Special Function Register at 7Ch and Bits [7:0] of the Configuration Register at 7Fh, which become
write-only registers in this mode.
6.7
Analog Voltage Measurement
The Hardware Monitor Block contains inputs for directly monitoring the power supplies (Vccp, and
VCC). These inputs are scaled internally to an internal reference source, converted via an 8 bit
successive approximation register ADC , and scaled such that the correct value refers to 3/4 scale or
192 decimal. The VCCP input is scaled for a full range of 0V to 3V.
Table 6.4 Low Power Mode Control Bits
START
LPMD
DESCRIPTION
0
0
Sleep Mode
0
1
Shutdown Mode
1
x
Monitoring


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