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AM29DS32XG Datasheet(PDF) 4 Page - SPANSION

Part No. AM29DS32XG
Description  32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation Flash Memory
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Maker  SPANSION [SPANSION]
Homepage  http://www.spansion.com
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AM29DS32XG Datasheet(HTML) 4 Page - SPANSION

 
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May 15, 2002
Am29DS32xG
3
ADV ANC E
INFO RMAT ION
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Special Handling Instructions for FBGA Package .......................... 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Device Bus Operations ...........................................................10
Word/Byte Configuration .............................................................. 10
Requirements for Reading Array Data ......................................... 10
Writing Commands/Command Sequences .................................. 11
Accelerated Program Operation ...................................................11
Autoselect Functions .................................................................... 11
Simultaneous Read/Write Operations
with Zero Latency ......................................................................... 11
Standby Mode .............................................................................. 11
Automatic Sleep Mode ................................................................. 11
RESET#: Hardware Reset Pin .....................................................12
Output Disable Mode ................................................................... 12
Table 2. Device Bank Divisions .............................................................12
Table 3. Top Boot Sector Addresses ...................................................13
Table 4. Top Boot SecSi
TM Sector Addresses ..................................... 14
Table 5. Bottom Boot Sector Addresses ...............................................16
Table 6. Bottom Boot SecSi
TM Sector Addresses ................................ 17
Autoselect Mode .......................................................................... 18
Table 7. Autoselect Codes, (High Voltage Method) .............................18
Sector/Sector Block Protection and Unprotection ........................ 19
Table 8. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection ...................................................................19
Table 9. Bottom Boot Sector/Sector Block Addresses
for Protection/Unprotection ...................................................................19
Write Protect (WP#) ..................................................................... 20
Temporary Sector Unprotect ........................................................ 20
Figure 1. Temporary Sector Unprotect Operation................................. 20
Figure 2. In-System Sector Protection/
Sector Unprotection Algorithms ............................................................ 21
SecSi
TM (Secured Silicon) Sector
Flash Memory Region .................................................................. 22
Factory Locked: SecSi Sector Programmed and Protected At the
Factory ......................................................................................... 22
Customer Lockable: SecSi Sector NOT Programmed or Protected At
the Factory ...................................................................................22
Hardware Data Protection ............................................................ 22
Low VCC Write Inhibit .................................................................. 23
Write Pulse “Glitch” Protection .....................................................23
Logical Inhibit ...............................................................................23
Power-Up Write Inhibit ................................................................. 23
Common Flash Memory Interface (CFI) . . . . . . . 23
Table 10. CFI Query Identification String .............................................. 23
Table 11. System Interface String......................................................... 24
Table 12. Device Geometry Definition .................................................. 24
Table 13. Primary Vendor-Specific Extended Query ............................ 25
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 25
Reading Array Data ...................................................................... 25
Reset Command .......................................................................... 26
Autoselect Command Sequence ..................................................26
Enter SecSi
TM Sector/Exit SecSi Sector
Command Sequence ................................................................... 26
Byte/Word Program Command Sequence ................................... 26
Unlock Bypass Command Sequence ........................................... 27
Figure 3. Program Operation ................................................................ 27
Chip Erase Command Sequence ................................................. 27
Sector Erase Command Sequence .............................................. 28
Erase Suspend/Erase Resume Commands ................................ 28
Figure 4. Erase Operation .................................................................... 29
Table 14. Command Definitions ........................................................... 30
Write Operation Status . . . . . . . . . . . . . . . . . . . . 31
DQ7: Data# Polling ...................................................................... 31
Figure 5. Data# Polling Algorithm ......................................................... 31
RY/BY#: Ready/Busy# ................................................................. 32
DQ6: Toggle Bit I .......................................................................... 32
Figure 6. Toggle Bit Algorithm .............................................................. 32
DQ2: Toggle Bit II ......................................................................... 33
Reading Toggle Bits DQ6/DQ2 .................................................... 33
DQ5: Exceeded Timing Limits ...................................................... 33
DQ3: Sector Erase Timer ............................................................. 33
Table 15. Write Operation Status ......................................................... 34
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 35
Figure 7. Maximum Negative Overshoot Waveform ............................. 35
Figure 8. Maximum Positive Overshoot Waveform .............................. 35
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 9. I
CC1 Current vs. Time (Showing Active and
Automatic Sleep Currents).................................................................... 37
Figure 10. Typical I
CC1 vs. Frequency................................................... 37
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 11. Test Setup .......................................................................... 38
Figure 12. Input Waveforms and Measurement Levels ........................ 38
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 13. Read Operation Timings...................................................... 39
Figure 14. Reset Timings...................................................................... 40
Word/Byte Configuration (BYTE#) ............................................... 41
Figure 15. BYTE# Timings for Read Operations .................................. 41
Figure 16. BYTE# Timings for Write Operations .................................. 41
Erase and Program Operations ................................................... 42
Figure 17. Program Operation Timings ................................................ 43
Figure 18. Accelerated Program Timing Diagram ................................ 43
Figure 19. Chip/Sector Erase Operation Timings ................................. 44
Figure 20. Back-to-back Read/Write Cycle Timings ............................. 45
Figure 21. Data# Polling Timings (During Embedded Algorithms) ....... 45
Figure 22. Toggle Bit Timings (During Embedded Algorithms) ............ 46
Figure 23. DQ2 vs. DQ6 ....................................................................... 46
Temporary Sector Unprotect ........................................................ 47
Figure 24. Temporary Sector Unprotect Timing Diagram ..................... 47
Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram 48
Alternate CE# Controlled Erase and Program Operations ........... 49
Figure 26. Alternate CE# Controlled Write (Erase/Program)
Operation Timings ................................................................................ 50
Erase And Programming Performance . . . . . . . 51
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 51
TSOP And SO Pin Capacitance . . . . . . . . . . . . . . 51
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
..................................................................................................... 51
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 52
FBD048—Fine-Pitch Ball Grid Array, 6 x 12 mm ......................... 52
TS 048—Thin Small Outline Package .......................................... 53
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 54
Revision A (May 15, 2002) ........................................................... 54


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