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AM41PDS3224DB70IT Datasheet(PDF) 14 Page - Advanced Micro Devices |
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AM41PDS3224DB70IT Datasheet(HTML) 14 Page - Advanced Micro Devices |
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14 / 59 page  May 13, 2002 Am41PDS3224D 13 P R E L IMINARY and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the ACC pin returns the device to normal op- eration. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- l e c t Comm and S equenc e s e c t i ons f o r m o r e information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location wi th in the same bank (e xce pt the s ector bei ng erased). Figure 21 shows how read and write cycles may be initiated for simultaneous operation with zero latency. I CC6 and ICC7 in the Flash DC Characteristics tabl e r epr es ent the c u r r ent s pec i f i c ati ons fo r r e a d - w hi l e - p r o gr am and r e ad- wh i l e- er as e, respectively. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE#f and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE#f and R ESET# are held at VIH , but not within V CC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The de- vice requires standard access time (t CE ) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- mi ng, the devic e draws active c urr ent until the operation is completed. I CC3 in the Flash DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard ad- dress access timings provide new data when ad- dresses are changed. While in sleep mode, output data is latched and always available to the system. Automatic sleep mode current is drawn when CE# = V SS ± 0.3 V and all inputs are held at VCC ± 0.3 V. If CE# and RESET# voltages are not held within these tolerances, the automatic sleep mode current will be greater. I CC5f in the Flash DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS ± 0.3 V, the de- vice draws CMOS standby current (I CC3f). If RESET# is held at V IL but not within VSS ± 0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase op- eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The sy stem can thus mon itor RY /B Y# to de term ine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not ex- ecuting (RY/BY# pin is “1”), the reset operation is com- pleted within a time of t READY (not during Embedded Algorithms). The system can read data t RH after the RESET# pin returns to V IH. Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 17 for the timing diagram. Output Disable Mode When the OE# input is at V IH, output from the device is disabled. The output pins are placed in the high impedance state. |
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