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AM42BDS640AG Datasheet(PDF) 64 Page - Advanced Micro Devices |
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AM42BDS640AG Datasheet(HTML) 64 Page - Advanced Micro Devices |
64 / 72 page November 1, 2002 Am42BDS640AG 63 P R E L I M INARY SRAM AC CHARACTERISTICS Read Cycle Note: CE1#s = OE# = V IL, CE2s = WE# = VIH, UB#s and/or LB#s = VIL Figure 34. SRAM Read Cycle—Address Controlled Parameter Symbol Description D8, D9 (54 MHz) C8, C9 (40 MHz) Unit t RC Read Cycle Time Min 70 85 ns t AA Address Access Time Max 70 85 ns t CO1, tCO2 Chip Enable to Output Max 70 85 ns t OE Output Enable Access Time Max 35 40 ns t BA LB#s, UB#s to Access Time Max 70 85 ns t LZ1, tLZ2 Chip Enable (CE1#s Low and CE2s High) to Low-Z Output Min 10 ns t BLZ UB#, LB# Enable to Low-Z Output Min 10 ns t OLZ Output Enable to Low-Z Output Min 5 ns t HZ1, tHZ2 Chip Disable to High-Z Output Max 25 ns t BHZ UB#s, LB#s Disable to High-Z Output Max 25 ns t OHZ Output Disable to High-Z Output Max 25 ns t OH Output Data Hold from Address Change Min 10 ns Address Data Out Previous Data Valid Data Valid tAA tRC tOH |
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