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AM42BDS640AG Datasheet(PDF) 31 Page - Advanced Micro Devices |
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AM42BDS640AG Datasheet(HTML) 31 Page - Advanced Micro Devices |
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31 / 72 page  30 Am42BDS640AG November 1, 2002 P R E L I M INARY Command Definitions Table 14. Command Definitions Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the rising edge of the AVD# pulse. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# pulse. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A21–A14 uniquely select any sector. BA = Address of the bank (A21, A20) that is being switched to autoselect mode, is in bypass mode, or is being erased. SLA = Address of the sector to be locked. Set sector address (SA) and either A6 = 1 for unlocked or A6 = 0 for locked. CR = Configuration Register address bits A19–A12. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD. 5. Unless otherwise noted, address bits A21–A12 are don’t cares. 6. No unlock or command cycles required when bank is reading array data. 7. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock. 8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address. See the Autoselect Command Sequence section for more information. 9. The data in the fifth cycle is 2204h for top boot, 2224h for bottom boot. 10. The data is 0000h for an unlocked sector and 0001h for a locked sector 11. The data is 0043h for reduced wait-state handshaking and 0042h standard handshaking. 12. The Unlock Bypass command sequence is required prior to this command sequence. 13. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. 14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 15. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. See “Set Burst Mode Configuration Register Command Sequence” for details. 17. Command is valid when device is ready to read array data or when device is in autoselect mode. Command Sequence (Notes) Bus Cycles (Notes 1–5) First Second Third Fourth Fifth Sixth Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Asynchronous Read (6) 1 RA RD Reset (7) 1 XXX F0 Manufacturer ID 4 555 AA 2AA 55 (BA)555 90 (BA)X00 0001 Device ID (9) 6 555 AA 2AA 55 (BA)555 90 (BA)X01 227E (BA) X0E (Note 9) (BA) X0F 2201 Sector Lock Verify (10) 4 555 AA 2AA 55 (SA)555 90 (SA)X02 0000/0001 Handshaking Option (11) 4 555 AA 2AA 55 (BA)555 90 (BA)X03 0042/0043 Program 4 555 AA 2AA 55 555 A0 PA PD Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass Program (12) 2 XXX A0 PA PD Unlock Bypass Sector Erase (12) 2 XXX 80 SA 30 Unlock Bypass Chip Erase (12) 2 XXX 80 XXX 10 Unlock Bypass Reset (13) 2 BA 90 XXX 00 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 Erase Suspend (14) 1 BA B0 Erase Resume (15) 1 BA 30 Sector Lock/Unlock 3 XXX 60 XXX 60 SLA 60 Set Burst Mode Configuration Register (16) 3 555 AA 2AA 55 (CR)555 C0 CFI Query (17) 1 55 98 |
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