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AM41PDS3224DB11IS Datasheet(PDF) 57 Page - Advanced Micro Devices |
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AM41PDS3224DB11IS Datasheet(HTML) 57 Page - Advanced Micro Devices |
57 / 59 page 56 Am41PDS3224D May 13, 2002 P R E L IMINARY SRAM DATA RETENTION Notes: 1. CE1#s ≥ V CC – 0.2 V, CE2s ≥ VCC – 0.2 V (CE1#s controlled) or CE2s ≤ 0.2 V (CE2s controlled), CIOs = VSS or VCC. 2. Typical values are not 100% tested. Figure 33. CE1#s Controlled Data Retention Mode Figure 34. CE2s Controlled Data Retention Mode Parameter Symbol Parameter Description Test Setup Min Typ Max Unit VDR VCC for Data Retention CS1#s ≥ V CC – 0.2 V (Note 1) 1.0 2.2 V I DR Data Retention Current VCC = 3.0 V, CE1#s ≥ VCC – 0.2 V (Note 1) 0.5 (Note 2) 3µA t SDR Data Retention Set-Up Time See data retention waveforms 0ns t RDR Recovery Time t RC ns VDR VCC 1.8V 1.4V CE1#s GND Data Retention Mode CE1#s ≥ VCC - 0.2 V tSDR tRDR VCC 1.8 V 0.4 V VDR CE2s GND Data Retention Mode tSDR tRDR CE2s < 0.2 V |
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