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AM42DL32X4G Datasheet(PDF) 3 Page - Advanced Micro Devices

Part No. AM42DL32X4G
Description  32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (256 K x 16-Bit) Static RAM
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Maker  AMD [Advanced Micro Devices]
Homepage  http://www.amd.com
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AM42DL32X4G Datasheet(HTML) 3 Page - Advanced Micro Devices

 
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 3 / 64 page
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May 19, 2003
Am42DL32x4G
3
PR ELI M I NARY
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . 7
Special Handling Instructions for FBGA Package .................... 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10
Table 2. Device Bus Operations—Flash Byte Mode, CIOf = V
SS ....12
Requirements for Reading Array Data ................................... 13
Writing Commands/Command Sequences ............................ 13
Accelerated Program Operation ............................................. 13
Autoselect Functions .............................................................. 13
Simultaneous Read/Write Operations with Zero Latency ....... 13
Automatic Sleep Mode ........................................................... 14
RESET#: Hardware Reset Pin ............................................... 14
Output Disable Mode .............................................................. 14
Table 3. Device Bank Division ........................................................14
Table 4. Top Boot Sector Addresses .............................................15
Sector/Sector Block Protection and Unprotection .................. 19
Table 8. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................19
Table 9. Bottom Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................20
Write Protect (WP#) ................................................................ 20
Temporary Sector/Sector Block Unprotect ............................. 20
Figure 1. Temporary Sector Unprotect Operation........................... 21
Figure 1. In-System Sector/Sector Block Protect and Unprotect
Algorithms ....................................................................................... 22
SecSi (Secured Silicon) Sector Flash Memory Region .......... 23
Factory Locked: SecSi Sector Programmed and Protected At the
Factory .................................................................................... 23
Customer Lockable: SecSi Sector NOT Programmed or
Protected At the Factory ......................................................... 23
Figure 2. SecSi Sector Protect Verify.............................................. 23
Hardware Data Protection ...................................................... 24
Low V
CC Write Inhibit .............................................................. 24
Write Pulse “Glitch” Protection ............................................... 24
Logical Inhibit .......................................................................... 24
Power-Up Write Inhibit ............................................................ 24
Common Flash Memory Interface (CFI) . . . . . . . 24
Command Definitions . . . . . . . . . . . . . . . . . . . . . 27
Reading Array Data ................................................................ 27
Reset Command ..................................................................... 27
Autoselect Command Sequence ............................................ 27
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 28
Byte/Word Program Command Sequence ............................. 28
Unlock Bypass Command Sequence ..................................... 28
Figure 3. Program Operation .......................................................... 29
Chip Erase Command Sequence ........................................... 29
Sector Erase Command Sequence ........................................ 29
Erase Suspend/Erase Resume Commands ........................... 30
Figure 4. Erase Operation............................................................... 30
Table 15. Autoselect Device IDs (Word Mode) ...............................31
Table 17. Autoselect Device IDs (Byte Mode) ................................32
Write Operation Status . . . . . . . . . . . . . . . . . . . . 33
DQ7: Data# Polling ................................................................. 33
Figure 5. Data# Polling Algorithm ................................................... 33
DQ6: Toggle Bit I .................................................................... 34
Figure 6. Toggle Bit Algorithm........................................................ 34
DQ2: Toggle Bit II ................................................................... 35
Reading Toggle Bits DQ6/DQ2 ............................................... 35
DQ5: Exceeded Timing Limits ................................................ 35
DQ3: Sector Erase Timer ....................................................... 35
Table 18. Write Operation Status ................................................... 36
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 37
Industrial (I) Devices ............................................................... 37
V
CCf/VCCs Supply Voltage ....................................................... 37
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38
CMOS Compatible .................................................................. 38
SRAM DC and Operating Characteristics. . . . . . 39
Zero-Power Flash ................................................................. 40
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep
Currents) ........................................................................................ 40
Figure 10. Typical I
CC1 vs. Frequency ............................................ 40
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 11. Test Setup.................................................................... 41
Table 19. Test Specifications ......................................................... 41
Key To Switching Waveforms . . . . . . . . . . . . . . . 41
Figure 12. Input Waveforms and Measurement Levels ................. 41
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42
SRAM CE#s Timing ................................................................ 42
Figure 13. Timing Diagram for Alternating Between SRAM to Flash ..
42
Flash Read-Only Operations ................................................. 43
Figure 14. Read Operation Timings ............................................... 43
Hardware Reset (RESET#) .................................................... 44
Figure 15. Reset Timings ............................................................... 44
Flash Word/Byte Configuration (CIOf) .................................... 45
Figure 16. CIOf Timings for Read Operations................................ 45
Figure 17. CIOf Timings for Write Operations................................ 45
Flash Erase and Program Operations .................................... 46
Figure 18. Program Operation Timings.......................................... 47
Figure 19. Accelerated Program Timing Diagram.......................... 47
Figure 20. Chip/Sector Erase Operation Timings .......................... 48
Figure 21. Back-to-back Read/Write Cycle Timings ...................... 49
Figure 22. Data# Polling Timings (During Embedded Algorithms). 49
Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... 50
Figure 24. DQ2 vs. DQ6................................................................. 50
Temporary Sector/Sector Block Unprotect ............................. 51
Figure 25. Temporary Sector/Sector Block Unprotect
Timing Diagram.............................................................................. 51
Figure 26. Sector/Sector Block Protect and Unprotect
Timing Diagram.............................................................................. 52
Alternate CE#f Controlled Erase and Program Operations .... 53
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings.......................................................................... 54
SRAM Read Cycle .................................................................. 55
Figure 28. SRAM Read Cycle—Address Controlled...................... 55
Figure 29. SRAM Read Cycle ........................................................ 56
SRAM Write Cycle .................................................................. 57
Figure 30. SRAM Write Cycle—WE# Control ................................ 57
Figure 31. SRAM Write Cycle—CE1#s Control ............................. 58
Figure 32. SRAM Write Cycle—UB#s and LB#s Control ............... 59
Flash Latchup Characteristics. . . . . . . . . . . . . . . 60
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 60
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 60
SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . . 61


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