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AM29BDS643GT5GVAI Datasheet(PDF) 11 Page - Advanced Micro Devices |
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AM29BDS643GT5GVAI Datasheet(HTML) 11 Page - Advanced Micro Devices |
11 / 49 page May 8, 2006 25692A2 Am29BDS643G 9 D A TA SH EE T DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register it- self does not occupy any addressable memory loca- tion. The register is composed of latches that store the commands, along with the address and data informa- tion needed to execute the command. The contents of the register serve as inputs to the internal state ma- chine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. Device Bus Operations Legend: L = Logic 0, H = Logic 1, X = Don’t Care. Requirements for Asynchronous Read Operation (Non-Burst) To read data from the memory array, the system must asser t a valid address on A/DQ0–A/DQ15 and A16–A21, while AVD# and CE# are at VIL. WE# should remain at VIH. Note that CLK must not be switching during asynchronous read operations. The rising edge of AVD# latches the address, after which the system can drive OE# to VIL. The data will appear on A/DQ0–A/DQ15. (See Figure 11.) Since the mem- ory array is divided into four banks, each bank remains enabled for read access until the command register contents are altered. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data at the outputs. The output enable access time (tOE) is the delay from the falling edge of OE# to valid data at the output. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. Requirements for Synchronous (Burst) Read Operation The device is capable of four different burst read modes (see Table 8): continuous burst read; and 8-, 16-, and 32-word linear burst reads with wrap around capability. Continuous Burst When the device first powers up, it is enabled for asyn- chronous read operation. The device will automatically be enabled for burst mode on the first rising edge on the CLK input, while AVD# is held low for one clock cycle. Prior to activating the clock signal, the system should determine how many wait states are desired for the initial word (tIACC) of each burst session. The system would then write the Set Configuration Register command sequence. The system may optionally acti- vate the PS mode (see “Power Saving Function”) by writing the Enable PS Mode command sequence at this time, but note that the PS mode can only be dis- abled by a hardware reset. (See “Command Defini- Operation CE# OE# WE# A16–21 A/DQ0–15 RESET# CLK AVD# Asynchronous Read L L H Addr In I/O H H/L Write L H L Addr In I/O H H/L Standby (CE#) H X X X HIGH Z H H/L X Hardware Reset X X X X HIGH Z L X X Burst Read Operations Load Starting Burst Address L H H Addr In Addr In H Advance Burst to next address with appropriate Data presented on the Data Bus LL H X Burst Data Out HH Terminate current Burst read cycle H X H X HIGH Z H X Terminate current Burst read cycle via RESET# X X H X HIGH Z L X X Terminate current Burst read cycle and start new Burst read cycle L H H X I/O H |
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