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AM41DL1624DT35IS Datasheet(PDF) 33 Page - Advanced Micro Devices |
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AM41DL1624DT35IS Datasheet(HTML) 33 Page - Advanced Micro Devices |
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33 / 63 page  32 Am41DL16x4D P R E L IMINARY WRITE OPERATION STATUS The device provides several bits to determine the sta- tus of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 20 and the following subsec- tions describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a pro- gram or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host sys- tem whether an Embedded Pr ogr am or E r as e algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum pro- grammed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Em- bedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns to reading array data. During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status infor- mation on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Poll- ing on DQ7 is active for approximately 100 µs, then the bank returns to reading array data. If not all se- lected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has com- pleted the program or erase operation and DQ7 has valid data, the data outputs on DQ0–DQ6 may be still invalid. Valid data on DQ0–DQ7 will appear on suc- cessive read cycles. Table 20 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data# Polling algorithm. Figure 22 in the AC Characteristics section shows the Data# Polling timing diagram. Figure 5. Data# Polling Algorithm DQ7 = Data? Yes No No DQ5 = 1? No Yes Yes FAIL PASS Read DQ7–DQ0 Addr = VA Read DQ7–DQ0 Addr = VA DQ7 = Data? START Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. |
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