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AM41DL16X4D Datasheet(PDF) 5 Page - Advanced Micro Devices

Part No. AM41DL16X4D
Description  16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (512 K x 8-Bit/256 K x 16-Bit) Static RAM
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Maker  AMD [Advanced Micro Devices]
Homepage  http://www.amd.com
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AM41DL16X4D Datasheet(HTML) 5 Page - Advanced Micro Devices

 
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Am41DL16x4D
P R E L IMINARY
Figure 22. Data# Polling Timings (During Embedded Algorithms).. 48
Figure 23. Toggle Bit Timings (During Embedded Algorithms)....... 49
Figure 24. DQ2 vs. DQ6.................................................................. 49
Temporary Sector/Sector Block Unprotect ............................. 50
Figure 25. Temporary Sector/Sector Block Unprotect
Timing Diagram............................................................................... 50
Figure 26. Sector/Sector Block Protect and Unprotect
Timing Diagram............................................................................... 51
Alternate CE#f Controlled Erase and Program Operations .... 52
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Op-
eration Timings................................................................................ 53
SRAM Read Cycle .................................................................. 54
Figure 28. SRAM Read Cycle—Address Controlled....................... 54
Figure 29. SRAM Read Cycle ......................................................... 55
SRAM Write Cycle .................................................................. 56
Figure 30. SRAM Write Cycle—WE# Control ................................. 56
Figure 31. SRAM Write Cycle—CE1#s Control ............................. 57
Figure 32. SRAM Write Cycle—UB#s and LB#s Control ............... 58
Flash Erase And Programming Performance
. 59
Flash Latchup Characteristics. . . . . . . . . . . . . . . 59
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 59
FLASH Data Retention . . . . . . . . . . . . . . . . . . . . . 59
SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 60
Figure 33. CE1#s Controlled Data Retention Mode....................... 60
Figure 34. CE2s Controlled Data Retention Mode......................... 60
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 61
FLA069—69-Ball Fine-Pitch Grid Array 8 x 11 mm ............... 61
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 62
Revision A (October 24, 2001) ............................................... 62


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