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AM29PL320D Datasheet(PDF) 4 Page - Advanced Micro Devices

Part No. AM29PL320D
Description  32 Megabit (2 M x 16-Bit/1 M x 32-Bit) CMOS 3.0 Volt-only High Performance Page Mode Flash Memory
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Maker  AMD [Advanced Micro Devices]
Homepage  http://www.amd.com
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AM29PL320D Datasheet(HTML) 4 Page - Advanced Micro Devices

 
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Am29PL320D
June 13, 2005
GENERAL DESCRIPTION
The Am29PL320D is a 32 Mbit, 3.0 Volt-only page
mode Flash memory device organized as 2,097,152
words or 1,048,576 double words. The device is of-
fered in an 84-ball FBGA package. The word-wide
data (x16) appears on DQ15–DQ0; the double word-
wide (x32) data appears on DQ31–DQ0. The device is
available in both top and bottom boot versions. This
device can be programmed in-system or with in stan-
dard EPROM programmers. A 12.0 V VPP or 5.0 VCC
are not required for write or erase operations.
The device offers fast page access times of 20, 25,
and 35 ns, with corresponding random access times of
60, 70, 90 ns, respectively, allowing high speed micro-
processors to operate without wait states. To eliminate
bus contention the device has separate chip enable
(CE#), write enable (WE#), and output enable (OE#)
controls.
Page Mode Features
The device is AC timing, input, output, and package
compatible with 16 Mbit x 16 page mode Mask
ROM. The page size is 8 words or 4 double words.
After initial page access is accomplished, the page
mode operation provides fast read access speed of
random locations within that page.
Standard Flash Memory Features
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Inter nally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write cy-
cles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algor ithm—an inter nal alg orithm that
automatically times the program pulse widths and
verifies proper cell margin. The Unlock Bypass mode
facilitates faster programming times by requiring only
two write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase,
the device automatically times the erase pulse widths
and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7
(Data# Polling) and DQ6 (toggle) status bits. After a
program or erase cycle has been completed, the device
is ready to read array data or accept another command.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
or y. Thi s c an be ac hie v ed in-s y s t e m or v i a
programming equipment.
The Erase Suspend/Erase Resume feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
The SecSi
™ Sector (Secured Silicon) is an extra sec-
tor capable of being permanently locked by AMD or
customers. The SecSi Indicator Bit (DQ7) is perma-
nently set to a 1 if the part is factory locked, and set
to a 0 if customer lockable. This way, customer lock-
able parts can never be used to replace a factory
locked par t. Current version of device has 512
words (256 double words); future versions will
have only 128 words (64 double words). This
should be considered during system design. Fac-
tory locked parts can store a secure, random 16 byte
ESN (Electronic Serial Number), customer code (pro-
grammed through AMD’s ExpressFlash service), or
both. Customer Lockable parts may be programmed
after being shipped from AMD.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.


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