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AM29BL802C Datasheet(PDF) 25 Page - Advanced Micro Devices |
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AM29BL802C Datasheet(HTML) 25 Page - Advanced Micro Devices |
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25 / 46 page  November 3, 2006 22371C7 Am29BL802C 23 D A TA SH EET must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 8). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously pro- grammed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the operation has ex- ceeded the timing limits, DQ5 produces a “1.” Under both these conditions, the system must issue the reset command to return the device to reading array data. DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from “0” to “1.” The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 μs. See also the “Sector Erase Command Sequence” section. After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Poll- ing) or DQ6 (Toggle Bit I) to ensure the device has ac- cepted the command sequence, and then read DQ3. If DQ3 is “1”, the internally controlled erase cycle has be- gun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0”, the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been ac- cepted. Table 5 shows the outputs for DQ3. START No Yes Yes DQ5 = 1? No Yes DQ6 = Toggle? No Read Byte (DQ0-DQ7) Address = VA DQ6 = Toggle? Read Byte Twice (DQ 0-DQ7) Adrdess = VA Read Byte (DQ0-DQ7) Address = VA FAIL PASS Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. See text. Figure 8. Toggle Bit Algorithm (Note 1) (Notes 1, 2) |
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