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AM29PL160C Datasheet(PDF) 4 Page - Advanced Micro Devices

Part No. AM29PL160C
Description  16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only High Performance Page Mode Flash Memory
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Maker  AMD [Advanced Micro Devices]
Homepage  http://www.amd.com
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AM29PL160C Datasheet(HTML) 4 Page - Advanced Micro Devices

 
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Am29PL160C
22143C7 May 9, 2006
D A TA
SH EE T
GENERAL DESCRIPTION
The Am29PL160C is a 16 Mbit, 3.0 Volt-only Page
mode Flash memory device organized as 2,097,152
bytes or 1,048,576 words.The device is offered in a 44-
pin SO or a 48-pin TSOP package. The word-wide
data (x16) appears on DQ15–DQ0; the byte-wide (x8)
data appears on DQ7–DQ0. This device can be pro-
g r am me d
in - s yst e m
or
wit h
i n
st an da r d
EPROM programmers. A 12.0 V VPP or 5.0 VCC are
not required for write or erase operations.
The device offers access times of 65, 70, and 90 ns, al-
lowing high speed microprocessors to operate without
wait states. To eliminate bus contention the device has
separate chip enable (CE#), write enable (WE#), and
output enable (OE#) controls.
The sector sizes are as follows: one 16 Kbyte, two
8 K by t e, on e 2 2 4 Kbyt e a n d seve n sect or s of
256 Kbytes each. The device is available in both top
and bottom boot versions.
Page Mode Features
The device is AC timing, pinout, and package compat-
ible with 16 Mbit x 16 page mode Mask ROM. The
page size is 8 words or 16 bytes.
After initial page access is accomplished, the page
mode operation provides fast read access speed of
random locations within that page.
Standard Flash Memory Features
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write cy-
cles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algor ithm—an inter nal algorithm that
automatically times the program pulse widths and
verifies proper cell margin. The Unlock Bypass mode
facilitates faster programming times by requiring only
two write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase,
the device automatically times the erase pulse widths
and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7
(Data# Polling) and DQ6 (toggle) status bits. After a
program or erase cycle has been completed, the device
is ready to read array data or accept another command.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
or y. This can be achie v ed in-syst em or via
programming equipment.
The Erase Suspend/Erase Resume feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.


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