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AM29F400B Datasheet(PDF) 4 Page - Advanced Micro Devices

Part No. AM29F400B
Description  4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory
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Maker  AMD [Advanced Micro Devices]
Homepage  http://www.amd.com
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AM29F400B Datasheet(HTML) 4 Page - Advanced Micro Devices

 
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Am29F400B
21505E5 November 1, 2006
D A TA
SH EE T
GENERAL DESCRIPTION
The Am29F400B is a 4 Mbit, 5.0 volt-only Flash
memory organized as 524,288 bytes or 262,144 words.
The device is offered in 44-pin SO and 48-pin TSOP
packages. The device is also available in Known Good
Die (KGD) form. For more information, refer to publica-
tion number 21258. The word-wide data (x16) appears
on DQ15–DQ0; the byte-wide (x8) data appears on
DQ7–DQ0. This device is designed to be programmed in-
system with the standard system 5.0 volt VCC supply. A 12.0
V VPP is not required for write or erase operations. The
device can also be programmed in standard EPROM
programmers.
This device is manufactured using AMD’s 0.32 µm
process technology, and offers all the features and ben-
efits of the Am29F400, which was manufactured using
0.5 µm process technology.
The standard device offers access times of 45, 50, 55,
70, 90, and 120 ns, allowing high speed microproces-
sors to operate without wait states. To eliminate bus
contention the device has separate chip enable (CE#),
write enable (WE#) and output enable (OE#) controls.
The device requires only a single 5.0 volt power
supply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase
command sequence. This initiates the Embedded
Erase algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6/
DQ2 (toggle) status bits. After a program or erase
cycle has been completed, the device is ready to read
array data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of memory.
This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the standby
mode. Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. The data is
programmed using hot electron injection.


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