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SN74GTLP817DWR Datasheet(PDF) 1 Page - Texas Instruments |
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SN74GTLP817DWR Datasheet(HTML) 1 Page - Texas Instruments |
1 / 19 page www.ti.com FEATURES DGV, DW, OR PW PACKAGE (TOP VIEW) AI AO1 GNDT AO2 VCC AO3 GNDT AO4 VCC AO5 GNDT AO6 GNDT OEAB BO1 GNDG VREF GNDG ERC BO2 GNDG BI OEBA GNDT 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 DESCRIPTION/ORDERING INFORMATION SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER SCES285E – OCTOBER 1999 – REVISED APRIL 2005 • OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference • Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels • GTLP-to-LVTTL 1-to-6 Fanout Driver • LVTTL-to-GTLP 1-to-2 Fanout Driver • LVTTL Interfaces Are 5-V Tolerant • Medium-Drive GTLP Outputs (50 mA) • Reduced-Drive LVTTL Outputs (–12 mA/12 mA) • Variable Edge-Rate Control (ERC) Input Selects GTLP Rise and Fall Times for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads • Ioff and Power-Up 3-State Support Hot Insertion • Distributed VCC and GND Pins Minimize High-Speed Switching Noise • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) The SN74GTLP817 is a medium-drive fanout driver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP reduced output swing (<1 V), reduced input threshold levels, improved differential input, and OEC™ circuitry. The improved GTLP OEC circuitry minimizes bus settling time and has been designed and tested using several backplane models. The medium drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 19 Ω. BO1 and BO2 can be tied together to drive an equivalent load impedance down to 11 Ω. GTLP is the Texas Instruments (TI™) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLP817 is given only at the preferred higher noise-margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels. Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input reference voltage. GNDT is the TTL output ground, while GNDG is the GTLP output ground, and both may be separated from each other for a quieter device. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. OEC, TI are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 1999–2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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